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1. 发明申请

US20140007098A1 PROCESSOR ACCELERATOR INTERFACE VIRTUALIZATION 审中-公开
标题翻译：处理器加速器界面虚拟化
公开(公告)号：US20140007098A1
公开(公告)日：2014-01-02
申请号：US13997379
申请日：2011-12-28
申请人： Paul M. Stillwell, JR. , Omesh Tickoo , Vineet Chadha , Yong Zhang , Rameshkumar G. Illikkal , Ravishankar Iyer
发明人： Paul M. Stillwell, JR. , Omesh Tickoo , Vineet Chadha , Yong Zhang , Rameshkumar G. Illikkal , Ravishankar Iyer
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F9/30003 , G06F9/45533
摘要： Embodiments of apparatuses and methods for processor accelerator interface virtualization are disclosed. In one embodiment, an apparatus includes instruction hardware and execution hardware. The instruction hardware is to receive instructions. One of the instruction types is an accelerator job request instruction type, which the execution hardware executes to cause the processor to submit a job request to an accelerator.
摘要翻译：公开了用于处理器加速器接口虚拟化的装置和方法的实施例。在一个实施例中，一种装置包括指令硬件和执行硬件。指令硬件是接收指令。指令类型之一是加速器作业请求指令类型，执行硬件执行以使处理器向加速器提交作业请求。

2. 发明授权

US08082418B2 Method and apparatus for coherent device initialization and access 有权
标题翻译：用于相干设备初始化和访问的方法和设备
公开(公告)号：US08082418B2
公开(公告)日：2011-12-20
申请号：US11958080
申请日：2007-12-17
申请人： Paul M. Stillwell, Jr. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
发明人： Paul M. Stillwell, Jr. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
IPC分类号： G06F15/00 , G06F15/76 , G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F9/3877 , G06F15/177 , G06F15/7867
摘要： A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.
摘要翻译：这里描述了一种用于使处理器插座中的加速器装置能够使用的方法和装置。使用一组处理器间消息来初始化加速器装置的配置/存储器空间。作为示例，发送第一组处理器间中断（IPI）以指示存储器空间的基址，并且发送第二组IPI以指示存储器空间的大小。此外，这里描述了类似的方法和装置，用于处理器插座中的加速器装置的动态重新配置。

3. 发明授权

US08473715B2 Dynamic accelerator reconfiguration via compiler-inserted initialization message and configuration address and size information 有权
标题翻译：通过编译器插入的初始化消息和配置地址和大小信息来动态加速器重新配置
公开(公告)号：US08473715B2
公开(公告)日：2013-06-25
申请号：US13160257
申请日：2011-06-14
申请人： Paul M. Stillwell, Jr. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
发明人： Paul M. Stillwell, Jr. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
IPC分类号： G06F15/00 , G06F15/76 , G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F9/3877 , G06F15/177 , G06F15/7867
摘要： A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.
摘要翻译：这里描述了一种用于使处理器插座中的加速器装置能够使用的方法和装置。使用一组处理器间消息来初始化加速器装置的配置/存储器空间。作为示例，发送第一组处理器间中断（IPI）以指示存储器空间的基址，并且发送第二组IPI以指示存储器空间的大小。此外，这里描述了类似的方法和装置，用于处理器插座中的加速器装置的动态重新配置。

4. 发明申请

US20110246691A1 METHOD AND APPARATUS FOR COHERENT DEVICE INITIALIZATION AND ACCESS 有权
标题翻译：用于相关设备初始化和访问的方法和装置
公开(公告)号：US20110246691A1
公开(公告)日：2011-10-06
申请号：US13160257
申请日：2011-06-14
申请人： Paul M. Stillwell, JR. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
发明人： Paul M. Stillwell, JR. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
IPC分类号： G06F13/36
CPC分类号： G06F9/3877 , G06F15/177 , G06F15/7867
摘要： A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.
摘要翻译：这里描述了一种用于使处理器插座中的加速器装置能够使用的方法和装置。使用一组处理器间消息来初始化加速器装置的配置/存储器空间。作为示例，发送第一组处理器间中断（IPI）以指示存储器空间的基址，并且发送第二组IPI以指示存储器空间的大小。此外，这里描述了类似的方法和装置，用于处理器插座中的加速器装置的动态重新配置。

5. 发明申请

US20100077179A1 METHOD AND APPARATUS FOR COHERENT DEVICE INITIALIZATION AND ACCESS 有权
标题翻译：用于相关设备初始化和访问的方法和装置
公开(公告)号：US20100077179A1
公开(公告)日：2010-03-25
申请号：US11958080
申请日：2007-12-17
申请人： Paul M. Stillwell, JR. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
发明人： Paul M. Stillwell, JR. , Nagabhushan Chitlur , Dennis Bradford , Linda Rankin
IPC分类号： G06F15/76 , G06F13/24 , G06F9/46 , G06F9/30
CPC分类号： G06F9/3877 , G06F15/177 , G06F15/7867
摘要： A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.
摘要翻译：这里描述了一种用于使处理器插座中的加速器装置能够使用的方法和装置。使用一组处理器间消息来初始化加速器装置的配置/存储器空间。作为示例，发送第一组处理器间中断（IPI）以指示存储器空间的基址，并且发送第二组IPI以指示存储器空间的大小。此外，这里描述了类似的方法和装置，用于处理器插座中的加速器装置的动态重新配置。

6. 发明申请

US20090089475A1 Low latency interface between device driver and network interface card 审中-公开
标题翻译：设备驱动程序与网络接口卡之间的低延迟接口
公开(公告)号：US20090089475A1
公开(公告)日：2009-04-02
申请号：US11906098
申请日：2007-09-28
申请人： Nagabhushan Chitlur , Linda Rankin , Paul M. Stillwell, JR. , Dennis Bradford
发明人： Nagabhushan Chitlur , Linda Rankin , Paul M. Stillwell, JR. , Dennis Bradford
IPC分类号： G06F13/14
CPC分类号： G06F13/28 , G06F13/102 , G06F13/385 , H04L49/90 , H04L49/9063
摘要： Methods and apparatus relating to a low latency interface between a device driver and a network interface device are described. In one embodiment, a network interface card (NIC) and a processor may be coupled through a coherent interconnection, e.g., to allow for coherent communication of data between buffers in the NIC and the processor. Other embodiments are also disclosed.
摘要翻译：描述了与设备驱动器和网络接口设备之间的低延迟接口有关的方法和设备。在一个实施例中，网络接口卡（NIC）和处理器可以通过相干互连耦合，例如，以允许在NIC和处理器中的缓冲器之间的数据的相干通信。还公开了其他实施例。

7. 发明授权

US06970942B1 Method of routing HTTP and FTP services across heterogeneous networks 有权
标题翻译：跨异构网络路由HTTP和FTP服务的方法
公开(公告)号：US06970942B1
公开(公告)日：2005-11-29
申请号：US09707428
申请日：2000-11-07
申请人： Steve King , Paul M. Stillwell, Jr. , Chiayin Mao
发明人： Steve King , Paul M. Stillwell, Jr. , Chiayin Mao
IPC分类号： H04L12/66 , H04L29/06 , H04L29/08 , H04L29/12 , G06F15/173
CPC分类号： H04L12/66 , H04L29/12594 , H04L61/30 , H04L67/02 , H04L69/08
摘要： A method and system for routing data across heterogeneous networks. In one embodiment, a heterogeneous network comprises a specialized in-band network that is privately accessible within the heterogeneous network, as well as an out-of-band network that is coupled to the in-band network by a switching platform. A client on the out-of-band network is configured to transmit a request for server data to the switching platform. The request is formatted according to the protocol of the out-of-band network and may take the form of a uniform resource locator (URL). The switching platform is configured to recognize the request as one which is directed to a server on the in-band network. The switching platform parses the request to determine the requested data and reformats this information as a new request that is transmitted to the server according to the protocol of the in-band network. The server provides data responsive to the new request, which is transmitted back to the switching platform according to the protocol of the in-band network. The switching platform then reformats the responsive data according to the protocol of the out-of-band network and transmits it to the client. The switching platform is separate from the default gateway and proxy servers.
摘要翻译：用于跨异构网络路由数据的方法和系统。在一个实施例中，异构网络包括在异构网络内私有可访问的专用带内网络，以及通过交换平台耦合到带内网络的带外网络。带外网络上的客户端被配置为向交换平台发送服务器数据请求。该请求根据带外网络的协议进行格式化，并且可以采用统一资源定位符（URL）的形式。交换平台被配置为将该请求识别为针对带内网络上的服务器的请求。交换平台解析请求以确定所请求的数据，并将该信息重新格式化为根据带内网络的协议传输到服务器的新请求。服务器提供响应于新请求的数据，根据带内网络的协议将其发送回交换平台。然后，交换平台根据带外网络的协议重新格式化响应数据，并将其发送给客户端。交换平台与默认网关和代理服务器是分开的。

8. 发明授权

US07996663B2 Saving and restoring architectural state for processor cores 有权
标题翻译：为处理器核心保存和恢复架构状态
公开(公告)号：US07996663B2
公开(公告)日：2011-08-09
申请号：US11965167
申请日：2007-12-27
申请人： Paul M. Stillwell, Jr. , Sorin Iacobovici , Moenes Iskarous
发明人： Paul M. Stillwell, Jr. , Sorin Iacobovici , Moenes Iskarous
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/384 , G06F9/3861 , G06F9/462
摘要： A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectural state is saved to memory in response to a save state triggering event, which may include a hardware event or a software event. Once saved, the state is potentially transferred to another processing element, such as a second core. As a result, hardware, software, or combination thereof may transfer architectural states between multiple processing elements, such as threads or cores, of a processor utilizing hardware support.
摘要翻译：描述了利用硬件来保存和恢复架构状态的方法和装置。处理元件（例如核心）的架构状态的第一部分在更新时被同时保存。响应于可能包括硬件事件或软件事件的保存状态触发事件，将结构状态的剩余部分保存到存储器。一旦保存，状态可能被转移到另一处理元件，例如第二核。结果，硬件，软件或其组合可以使用硬件支持在处理器的诸如线程或核心的多个处理元件之间传送架构状态。

9. 发明申请

US20090172369A1 SAVING AND RESTORING ARCHITECTURAL STATE FOR PROCESSOR CORES 有权
标题翻译：节省和恢复处理器的架构状态
公开(公告)号：US20090172369A1
公开(公告)日：2009-07-02
申请号：US11965167
申请日：2007-12-27
申请人： Paul M. Stillwell, JR. , Sorin Iacobovici , Moenes Iskarous
发明人： Paul M. Stillwell, JR. , Sorin Iacobovici , Moenes Iskarous
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/384 , G06F9/3861 , G06F9/462
摘要： A method and apparatus for saving and restoring architectural states utilizing hardware is herein described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectural state is saved to memory in response to a save state triggering event, which may include a hardware event or a software event. Once saved, the state is potentially transferred to another processing element, such as a second core. As a result, hardware, software, or combination thereof may transfer architectural states between multiple processing elements, such as threads or cores, of a processor utilizing hardware support.
摘要翻译：这里描述了利用硬件来保存和恢复架构状态的方法和装置。处理元件（例如核心）的架构状态的第一部分在更新时被同时保存。响应于可能包括硬件事件或软件事件的保存状态触发事件，将结构状态的剩余部分保存到存储器。一旦保存，状态可能被转移到另一处理元件，例如第二核。结果，硬件，软件或其组合可以使用硬件支持在处理器的诸如线程或核心的多个处理元件之间传送架构状态。

10. 发明授权

US07290114B2 Sharing data in a user virtual address range with a kernel virtual address range 失效
标题翻译：在用户虚拟地址范围内与内核虚拟地址范围共享数据
公开(公告)号：US07290114B2
公开(公告)日：2007-10-30
申请号：US10991717
申请日：2004-11-17
申请人： Paul M. Stillwell, Jr. , Vikram A. Saletore
发明人： Paul M. Stillwell, Jr. , Vikram A. Saletore
IPC分类号： G06F12/00
CPC分类号： G06F12/109 , G06F2212/656
摘要： Provided are a method, system, and program for sharing data in a user virtual address range with a kernel virtual address range. A user address in a user address space and length defining a user address range referencing physical locations in a memory are received. A determination is made of determining at least one page in the memory including the physical locations referenced by the user address range. For each determined page, one kernel address in a kernel address space is generated to reference the determined page, wherein at least one user address and at least one kernel address reference one page in the memory.
摘要翻译：提供了一种用于在具有内核虚拟地址范围的用户虚拟地址范围内共享数据的方法，系统和程序。接收用户地址空间中的用户地址和定义参考存储器中的物理位置的用户地址范围的长度。确定确定存储器中的至少一个页面，包括由用户地址范围引用的物理位置。对于每个确定的页面，生成内核地址空间中的一个内核地址以引用确定的页面，其中至少一个用户地址和至少一个内核地址引用存储器中的一页。

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