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1. 发明授权

US07933341B2 System and method for high speed communications using digital signal processing 有权
标题翻译：使用数字信号处理的高速通信系统和方法
公开(公告)号：US07933341B2
公开(公告)日：2011-04-26
申请号：US09797428
申请日：2001-02-28
申请人： Oscar E. Agazzi , Gottfried Ungerboeck , Keshab K. Parhi , Christian A. Lutkemeyer , Pieter Vorenkamp , Kevin T. Chan , Myles H. Wakayama
发明人： Oscar E. Agazzi , Gottfried Ungerboeck , Keshab K. Parhi , Christian A. Lutkemeyer , Pieter Vorenkamp , Kevin T. Chan , Myles H. Wakayama
IPC分类号： H04L25/02
CPC分类号： H04L25/4975 , G09G5/006 , G09G2370/18 , H03M1/0604 , H03M1/1215 , H04L25/03146 , H04L25/03343 , H04L25/497
摘要： Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.
摘要翻译：公开了与通信信道中的均衡预编码相关的各种系统和方法。在一个实现中，对通过光信道传输的信号执行以前的实现。在一个实现中，并行执行解码操作，以便于在相对低成本的电路中实现高速处理。可以通过发送与收发器对之间的信道的特性相关的信息来实现预编码器的初始化。

2. 发明授权

US07072633B2 Double-conversion television tuner using a Delta-Sigma Fractional-N PLL 失效
标题翻译：使用Delta-Sigma分数N PLL的双转换电视调谐器
公开(公告)号：US07072633B2
公开(公告)日：2006-07-04
申请号：US10366668
申请日：2003-02-14
申请人： Ramon A Gomez , Myles H Wakayama
发明人： Ramon A Gomez , Myles H Wakayama
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03L7/185 , H03D7/161 , H03L7/07 , H03L7/10 , H03L7/1976
摘要： A double-conversion tuner receives an RF signal having a number of channels and down-converts a selected channel from the plurality of channels. The double-conversion tuner includes a first mixer configured to up-convert the RF signal to a first IF signal using a first local oscillator signal. A first local oscillator includes a delta-sigma fractional-N phase lock loop to produce the first local oscillator signal. The delta-sigma fractional-N phase lock loop is configured to perform fine-tuning of the first local oscillator signal and to have a wide tuning range sufficient to cover the number of channels. A bandpass filter is configured to select a subset of channels from said first IF signal. A second mixer is configured to down-convert the subset of channels to a second IF signal using a second local oscillator signal. A second local oscillator generates the second local oscillator signal. The second local oscillator is configured to perform coarse frequency tuning of the second local oscillator signal and has a narrow tuning range relative to said first local oscillator. The delta-sigma fractional-N phase lock loop in the first local oscillator permits implementation of a double-conversion tuner with improved phase noise for a given amount of power and complexity.
摘要翻译：双转换调谐器接收具有多个信道的RF信号并且从多个信道中对所选择的信道进行下变频。双转换调谐器包括配置为使用第一本地振荡器信号将RF信号上变频到第一IF信号的第一混频器。第一本地振荡器包括Δ-sigma分数N相位锁相环以产生第一本地振荡器信号。 Δ-Σ分数N相锁定环路被配置为执行第一本地振荡器信号的微调并且具有足以覆盖通道数量的宽调谐范围。带通滤波器被配置为从所述第一IF信号中选择信道的子集。第二混频器被配置为使用第二本地振荡器信号将信道子集降频转换为第二IF信号。第二本地振荡器产生第二本地振荡器信号。第二本地振荡器被配置为执行第二本地振荡器信号的粗调频调谐，并且相对于所述第一本地振荡器具有窄的调谐范围。第一本地振荡器中的delta-sigma分数N相锁定环允许在给定量的功率和复杂度的情况下实现具有改进的相位噪声的双转换调谐器。

3. 发明授权

US08422591B2 System and method for high speed communications using digital signal processing 失效
标题翻译：使用数字信号处理的高速通信系统和方法
公开(公告)号：US08422591B2
公开(公告)日：2013-04-16
申请号：US13090379
申请日：2011-04-20
申请人： Oscar E. Agazzi , Gottfried Ungerboeck , Keshab K. Parhi , Christian A. Lutkemeyer , Pieter Vorenkamp , Kevin T. Chan , Myles H. Wakayama
发明人： Oscar E. Agazzi , Gottfried Ungerboeck , Keshab K. Parhi , Christian A. Lutkemeyer , Pieter Vorenkamp , Kevin T. Chan , Myles H. Wakayama
IPC分类号： H04L27/00
CPC分类号： H04L25/4975 , H03M1/0604 , H03M1/1215 , H04L25/03133 , H04L25/03146 , H04L25/03343 , H04L25/497 , H04L2025/03503
摘要： Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.
摘要翻译：公开了与通信信道中的均衡预编码相关的各种系统和方法。在一个实现中，对通过光信道发射的信号执行预编码。在一个实现中，并行执行预编码和解码操作以便于在相对低成本的电路中进行高速处理。可以通过发送与收发器对之间的信道的特性相关的信息来实现预编码器的初始化。

4. 发明授权

US07106388B2 Digital IF demodulator for video applications 失效
公开(公告)号：US07106388B2
公开(公告)日：2006-09-12
申请号：US09739349
申请日：2000-12-15
申请人： Pieter Vorenkamp , Myles H. Wakayama , Steven Jaffe , Frank Carr , Arnoldus Venes , Peter R. Kinget , Daniel J. Marz , Thinh Nguyen
发明人： Pieter Vorenkamp , Myles H. Wakayama , Steven Jaffe , Frank Carr , Arnoldus Venes , Peter R. Kinget , Daniel J. Marz , Thinh Nguyen
IPC分类号： H04N5/455
CPC分类号： H04N5/455 , H03D7/16 , H03J3/18 , H04N5/44
摘要： An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

5. 发明授权

US06897733B2 Low offset and low glitch energy charge pump for PLL-based timing recovery systems 有权
标题翻译：用于基于PLL的定时恢复系统的低偏移和低毛刺能量电荷泵
公开(公告)号：US06897733B2
公开(公告)日：2005-05-24
申请号：US09972019
申请日：2001-10-05
申请人： Myles H. Wakayama
发明人： Myles H. Wakayama
IPC分类号： H03L7/089 , H03L7/093
CPC分类号： H03L7/0898 , H03L7/0896
摘要： A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.
摘要翻译：设计并构造了一个结合了相位/频率检测器的锁相环中使用的高精度电荷泵，从而大大消除了电荷泵输出电流下直流偏移和毛刺误差的影响。高精度电荷泵由平行电流路径构成，每个电路具有中心节点，中心节点又连接到反馈元件。反馈元件定义了一个反馈电流，该电流被施加到电荷泵上，以便将两个中心节点保持在等电位电平，并且将降压电流的值保持正确地等于泵浦电流的值由设备输出。

6. 发明授权

US5243235A Sample-and-hold circuit 失效
标题翻译：样品保持电路
公开(公告)号：US5243235A
公开(公告)日：1993-09-07
申请号：US784872
申请日：1991-10-30
申请人： Myles H. Wakayama , Hiroshi Tanimoto
发明人： Myles H. Wakayama , Hiroshi Tanimoto
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： A sample-and-hold circuit comprising a diode circuit including four diodes connected in series, an input circuit connected to a first node of the first and third diodes and a second node of the second and fourth diodes, first and second output terminals connected to a third node of the first and second diodes and a fourth node of the third and fourth diodes, two capacitors connected to the third and fourth nodes, respectively, and a current mirror circuit having a first terminal connected to the input circuit, a second terminal connected to the first node, and a third terminal connected to the second node, for supplying to the second and third terminals, a DC bias current and a dynamic current corresponding to the slew rate of the input signal flowing through the first terminal of the current mirror circuit. The diode circuit charges the capacitor with the output current supplied from the current mirror circuit in accordance with the input signal, thereby to sample the input signal, and holds the charge in the capacitor upon completion of the charging of the capacitor, thereby to hold the input signal.

7. 发明授权

US08711288B2 Digital IF demodulator for video applications 有权
标题翻译：用于视频应用的数字IF解调器
公开(公告)号：US08711288B2
公开(公告)日：2014-04-29
申请号：US11516718
申请日：2006-09-07
申请人： Pieter Vorenkamp , Myles H. Wakayama , Steven Jaffe , Frank Carr , Arnoldus Venes , Peter R. Kinget , Daniel J. Marz , Thinh Nguyen
发明人： Pieter Vorenkamp , Myles H. Wakayama , Steven Jaffe , Frank Carr , Arnoldus Venes , Peter R. Kinget , Daniel J. Marz , Thinh Nguyen
IPC分类号： H04N5/44
CPC分类号： H04N5/455 , H03D7/16 , H03J3/18 , H04N5/44
摘要： An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
摘要翻译：综合通信系统。一种衬底，具有设置在衬底上的接收器，用于将接收信号转换成IF信号;数字IF解调器，设置在衬底上并耦合到接收器，用于将IF信号转换成解调的基带信号;以及发射器，设置在衬底上与接收方合作建立双向通信路径。

8. 发明申请

US20110206109A1 System and Method for High Speed Communications Using Digital Signal Processing 失效
标题翻译：使用数字信号处理的高速通信系统和方法
公开(公告)号：US20110206109A1
公开(公告)日：2011-08-25
申请号：US13090379
申请日：2011-04-20
申请人： Oscar E. Agazzi , Gottfried Ungerboeck , Keshab K. Parhi , Christian A. Lutkemeyer , Pieter Vorenkamp , Kevin T. Chan , Myles H. Wakayama
发明人： Oscar E. Agazzi , Gottfried Ungerboeck , Keshab K. Parhi , Christian A. Lutkemeyer , Pieter Vorenkamp , Kevin T. Chan , Myles H. Wakayama
IPC分类号： H04L27/06 , H04L27/00 , H03K5/159
CPC分类号： H04L25/4975 , H03M1/0604 , H03M1/1215 , H04L25/03133 , H04L25/03146 , H04L25/03343 , H04L25/497 , H04L2025/03503
摘要： Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.
摘要翻译：公开了与通信信道中的均衡预编码相关的各种系统和方法。在一个实现中，对通过光信道发射的信号执行预编码。在一个实现中，并行执行预编码和解码操作以便于在相对低成本的电路中进行高速处理。可以通过发送与收发器对之间的信道的特性相关的信息来实现预编码器的初始化。

9. 发明授权

US07057465B2 Low offset and low glitch energy charge pump and method of operating same 有权
标题翻译：低偏移和低毛刺能量电荷泵及其操作方法
公开(公告)号：US07057465B2
公开(公告)日：2006-06-06
申请号：US11102716
申请日：2005-04-11
申请人： Myles H. Wakayama
发明人： Myles H. Wakayama
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L7/0896
摘要： A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.
摘要翻译：设计并构造了一个结合了相位/频率检测器的锁相环中使用的高精度电荷泵，从而大大消除了电荷泵输出电流下直流偏移和毛刺误差的影响。高精度电荷泵由平行电流路径构成，每个电路具有中心节点，中心节点又连接到反馈元件。反馈元件定义了一个反馈电流，该电流被施加到电荷泵上，以便将两个中心节点保持在等电位电平，并且将降压电流的值保持正确地等于泵浦电流的值由设备输出。

10. 发明授权

US06829715B2 Multiprotocol computer bus interface adapter and method 有权
标题翻译：多协议计算机总线接口适配器和方法
公开(公告)号：US06829715B2
公开(公告)日：2004-12-07
申请号：US09865844
申请日：2001-05-25
申请人： Jennifer Y. Chiao , Gary A. Alvstad , Myles H. Wakayama
发明人： Jennifer Y. Chiao , Gary A. Alvstad , Myles H. Wakayama
IPC分类号： G06F104
CPC分类号： G06F1/10 , G06F2213/0024
摘要： A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.
摘要翻译：具有与同步器反馈延迟环耦合的预测同步器和复制延迟元件的预测时基发生器。预测时基发生器接收延迟了预定时钟延迟的时钟信号，并产生一个预测时间信号，该预测时间信号在时间上提前由复制延迟元件表示的量。复制延迟元件可以复制预定时钟延迟和预定数据延迟中的一个或两个，从而基本上使设备的关键信号路径中的相应延迟无效。复制延迟元件可以包括在输入时钟路径和输出数据路径中找到的结构的副本，这些元件包括例如电压电平移位器，缓冲器或数据锁存器，多路复用器，线元模型等。还提供了一种包含上述预测时基发生器的预测计算机总线接口适配器。这种预测接口适配器可以适应于遵守在PCI和PCI-X局部总线协议下施加的严格总线协议时序预算，并且相对于设计和制造过程以及环境操作条件的变化而言是稳健的。

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