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1. 发明申请

US20050270891A1 Backwards-compatible memory module 有权
公开(公告)号：US20050270891A1
公开(公告)日：2005-12-08
申请号：US11127536
申请日：2005-05-12
申请人： Bjorn Flach , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Bjorn Flach , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G11C5/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4093 , G11C11/4096
CPC分类号： G11C7/1078 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4096 , G11C2207/107
摘要： Memory module (1, 101, 201) having: at least one memory cell array (6, 106, 206), with the memory cells each being addressable by at least one address and being organized in organization units comprising a predetermined number of memory cells which can be driven jointly and at the same time; a clocked read/write control device (11, 111, 211), which is clocked with a first clock signal (CLK1) and which is coupled to the memory cell array (6, 106, 206), for writing data to and reading data from the memory cells as a function of address signals (ADR); a prefetch register unit (13, 113, 213), which is coupled to the read/write control device (11, 111, 211), for initial storage of data which is read from the memory cell array (6, 106, 206) and having two or more prefetch registers (14-17, 114-117, 214-217), whose respective register size corresponds to the predetermined number of memory cells in the organization units; a controlled switching device (23, 123, 223), which is coupled to the prefetch register unit (13, 113, 213), for outputting the data (DQs) which is initially stored in the prefetch registers (14-17, 114-117, 214-217) at data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201), with the switching device (23, 123, 223) successively coupling the prefetch registers (14-17, 114-117, 214-217) to the data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201) in a first operating mode of the memory module (1, 101, 201), controlled by a second clock signal (CLK2), with the number of data inputs/outputs (5, 105, 205) corresponding to the number of memory cells in the organization units, and coupling at least one of the prefetch registers (14-17, 114-117, 214-217) to the data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201) in a second operating mode controlled by at least one of the address signals (ADR).

2. 发明授权

US07221617B2 Backwards-compatible memory module 有权
标题翻译：向后兼容内存模块
公开(公告)号：US07221617B2
公开(公告)日：2007-05-22
申请号：US11127536
申请日：2005-05-12
申请人： Bjorn Flach , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Bjorn Flach , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G11C8/00
CPC分类号： G11C7/1078 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4096 , G11C2207/107
摘要： A backwards-compatible memory module is disclosed. According to one aspect, a memory module comprises addressable memory cells organized in organization units having a predetermined number of memory cells, a read/write control device clocked by a first clock signal, a plurality of prefetch registers for initially storing data read from the memory cells wherein the register size corresponds to the predetermined number. In a first operating mode, a switching device clocked by a second clock signal successively couples the prefetch registers to data input/output terminals. The number of data input/output terminals corresponds to the predetermined number. In a second operating mode, the switching device is controlled by at least one address signal and couples at least one of the prefetch registers to the data input/output terminals.
摘要翻译：公开了向后兼容的存储器模块。根据一个方面，一种存储器模块包括以具有预定数量的存储器单元的组织单元组织的可寻址存储器单元，由第一时钟信号定时的读/写控制装置，用于初始存储从存储器读取的数据的多个预取寄存器其中寄存器大小对应于预定数量的单元。在第一操作模式中，由第二时钟信号计时的开关器件将预取寄存器连续地耦合到数据输入/输出端子。数据输入/输出端子的数量对应于预定数量。在第二操作模式中，开关装置由至少一个地址信号控制，并将预取寄存器中的至少一个耦合到数据输入/输出端子。

3. 发明授权

US07414421B2 Insertable calibration device 失效
标题翻译：可插入校准装置
公开(公告)号：US07414421B2
公开(公告)日：2008-08-19
申请号：US11290138
申请日：2005-11-30
申请人： Björn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Björn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G01R31/02
CPC分类号： G01R35/005 , G11C29/56 , G11C2029/5602
摘要： An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result. The control unit evaluates the comparison results and can be used to program the transmission instants in such a way that the instants at which the calibration signal edge and the reference signal edge arrive, for the compensation of signal propagation time differences, are substantially identical. The calibration device has the same form and connections as the electric device and is insertable into the holding device with an accurate fit instead of the electronic device.
摘要翻译：用于可编程测试仪器的可插入校准装置包括至少一个校准单元和控制单元。可程序测试仪装置被配置为使用电子电路测试至少一个电子设备。可程序测试仪器包括保持装置，用于电子装置的接触装置和用于将信号耦合到电子装置的测试仪通道。校准单元连接到要校准的第一测试仪通道。校准单元被配置为检测在某一传输时刻由测试仪器发送的校准信号的校准信号边沿，以检测由测试仪器通过第二测试器通道发送的参考信号的参考信号边沿在参考时刻，比较两个信号边缘到达的时刻，并输出比较结果。控制单元评估比较结果，并且可以用于对传输时刻进行编程，使得校准信号边沿和参考信号边缘到达的时刻用于信号传播时间差的补偿基本相同。校准装置具有与电气装置相同的形式和连接，并且可以精确配合而不是电子装置插入到保持装置中。

4. 发明申请

US20060149491A1 Insertable calibration device 失效
标题翻译：可插入校准装置
公开(公告)号：US20060149491A1
公开(公告)日：2006-07-06
申请号：US11290138
申请日：2005-11-30
申请人： Bjorn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Bjorn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G06F19/00
CPC分类号： G01R35/005 , G11C29/56 , G11C2029/5602
摘要： An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result. The control unit evaluates the comparison results and can be used to program the transmission instants in such a way that the instants at which the calibration signal edge and the reference signal edge arrive, for the compensation of signal propagation time differences, are substantially identical. The calibration device has the same form and connections as the electric device and is insertable into the holding device with an accurate fit instead of the electronic device.
摘要翻译：用于可编程测试仪器的可插入校准装置包括至少一个校准单元和控制单元。可程序测试仪装置被配置为使用电子电路测试至少一个电子设备。可程序测试仪器包括保持装置，用于电子装置的接触装置和用于将信号耦合到电子装置的测试仪通道。校准单元连接到要校准的第一测试仪通道。校准单元被配置为检测在某一传输时刻由测试仪器发送的校准信号的校准信号边沿，以检测由测试仪器通过第二测试器通道发送的参考信号的参考信号边沿在参考时刻，比较两个信号边缘到达的时刻，并输出比较结果。控制单元评估比较结果，并且可以用于对传输时刻进行编程，使得校准信号边沿和参考信号边缘到达的时刻用于信号传播时间差的补偿基本相同。校准装置具有与电气装置相同的形式和连接，并且可以精确配合而不是电子装置插入到保持装置中。

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