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    • 1. 发明授权
    • Successive approximation register analog-digital converter and method for operating the same
    • 逐次逼近寄存器模数转换器及其操作方法
    • US08599059B1
    • 2013-12-03
    • US13617325
    • 2012-09-14
    • Yung-Hui ChungMeng-Hsuan Wu
    • Yung-Hui ChungMeng-Hsuan Wu
    • H03M1/12
    • H03M1/466
    • A SAR ADC converting an analog signal into a digital signal having N bits counting from a most significant bit to a least significant bit includes a comparator comparing a positive component with a negative component of the analog signal, two CDACs and a logic circuit. For at least one i-th bit cycle of N bit cycle except a least significant bit cycle, one of a pair of capacitors relating to (i+1)-th bit respectively arranged in the two CDACs is switched according to a first comparing result of the comparator. After one of the pair of capacitors is switched, the comparator compares the positive component with the negative component of the analog signal again and generates a second comparing result. Then whether each one of capacitors relating to i-th bit in the two CDAC is to be switched is determined according to the first and the second comparing result.
    • 将模拟信号转换为具有从最高有效位计数到最低有效位的N位的数字信号的SAR ADC包括比较正分量与模拟信号的负分量,两个CDAC和逻辑电路的比较器。 对于除了最低有效位周期之外的N位周期的至少一个第i个比特周期,与分别布置在两个CDAC中的与第(i + 1)比特相关的一对电容器中的一个电容器根据第一比较结果被切换 的比较器。 在一对电容器中的一个被切换之后,比较器再次将正分量与模拟信号的负分量进行比较,并产生第二比较结果。 然后根据第一和第二比较结果确定是否要切换与两个CDAC中的第i个位相关的每个电容器。
    • 3. 发明授权
    • Successive approximation register analog to digital converter and conversion method thereof
    • 逐次逼近寄存器模数转换器及其转换方法
    • US08508400B2
    • 2013-08-13
    • US13479021
    • 2012-05-23
    • Meng Hsuan WuYung-Hui Chung
    • Meng Hsuan WuYung-Hui Chung
    • H03M1/12
    • H03M1/0673H03M1/468
    • A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.
    • 提供了一个SAR ADC。 DAC根据模拟输入信号,最高有效位电容和小于最高有效位电容的多个有效位电容提供中间模拟信号。 第一开关电容器阵列根据选择信号选择性地提供最高有效位电容或有效位电容。 有效位电容的总和等于最高有效位电容。 当第一开关电容器阵列提供最高有效位电容时,第二开关电容器阵列提供有效位电容,并且当第一开关电容器阵列提供有效位电容时提供最高有效位电容。 比较器根据中间模拟信号提供比较结果。 SAR逻辑根据比较结果提供数字输出信号。
    • 5. 发明申请
    • SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF
    • 数字近似寄存器模拟数字转换器及其转换方法
    • US20120326900A1
    • 2012-12-27
    • US13479021
    • 2012-05-23
    • Meng Hsuan WUYung-Hui CHUNG
    • Meng Hsuan WUYung-Hui CHUNG
    • H03M1/38
    • H03M1/0673H03M1/468
    • A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.
    • 提供了一个SAR ADC。 DAC根据模拟输入信号,最高有效位电容和小于最高有效位电容的多个有效位电容提供中间模拟信号。 第一开关电容器阵列根据选择信号选择性地提供最高有效位电容或有效位电容。 有效位电容的总和等于最高有效位电容。 当第一开关电容器阵列提供最高有效位电容时,第二开关电容器阵列提供有效位电容,并且当第一开关电容器阵列提供有效位电容时提供最高有效位电容。 比较器根据中间模拟信号提供比较结果。 SAR逻辑根据比较结果提供数字输出信号。