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1. 发明授权

US08932915B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08932915B2
公开(公告)日：2015-01-13
申请号：US13082103
申请日：2011-04-07
申请人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L29/772 , H01L21/336 , B82Y10/00 , H01L21/84 , H01L27/06 , H01L27/115 , H01L27/12 , H01L29/04 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/792 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/66765 , B82Y10/00 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/092 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/0673 , H01L29/66439 , H01L29/66666 , H01L29/66833 , H01L29/775 , H01L29/7827 , H01L29/7843 , H01L29/7847 , H01L29/78669 , H01L29/78678 , H01L29/792
摘要： A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
摘要翻译：实施例的半导体器件制造方法包括以下步骤：在半导体衬底上形成第一绝缘层; 在第一绝缘层上形成具有窄部分的非晶或多晶半导体层; 在所述半导体层上形成具有大于所述半导体层的热膨胀系数的热膨胀系数的第二绝缘层; 进行热处理; 去除所述第二绝缘层; 在所述窄部的侧面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 以及在所述半导体层中形成源 - 漏区。

2. 发明授权

US08076231B2 Semiconductor device and manufacturing method of same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08076231B2
公开(公告)日：2011-12-13
申请号：US12401704
申请日：2009-03-11
申请人： Masumi Saitoh , Ken Uchida
发明人： Masumi Saitoh , Ken Uchida
IPC分类号： H01L21/4763
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L29/0673 , H01L29/0676 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.
摘要翻译：提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区，在其间插入通道区域。通道区域在与基板主平面垂直的方向上施加压缩应变。还公开了该装置的制造方法。

3. 发明申请

US20080149991A1 Non-volatile semiconductor storage device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US20080149991A1
公开(公告)日：2008-06-26
申请号：US11859142
申请日：2007-09-21
申请人： Masumi SAITOH , Ken UCHIDA
发明人： Masumi SAITOH , Ken UCHIDA
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变，并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

4. 发明授权

US08907406B2 Transistor having impurity distribution controlled substrate and method of manufacturing the same 有权
标题翻译：具有杂质分布受控衬底的晶体管及其制造方法
公开(公告)号：US08907406B2
公开(公告)日：2014-12-09
申请号：US13729959
申请日：2012-12-28
申请人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka , Yusuke Higashi
发明人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka , Yusuke Higashi
IPC分类号： H01L29/66 , H01L29/786 , H01L29/06 , H01L29/32 , B82Y40/00 , H01L29/775 , H01L29/78 , B82Y10/00
CPC分类号： H01L29/32 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78603 , H01L29/78696
摘要： A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.
摘要翻译：根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的掩埋绝缘层，形成在掩埋绝缘层上并且包括狭窄部分和比窄部分大的两个宽部分的半导体层并且分别连接到窄部分的一端和另一端，形成在窄部分的侧表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。直接在窄部下方的半导体衬底的杂质浓度高于窄部分的杂质浓度，并且直接在窄部下方的半导体衬底的杂质浓度高于直接在宽度以下的半导体衬底的杂质浓度一部分。

5. 发明申请

US20130240828A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130240828A1
公开(公告)日：2013-09-19
申请号：US13729959
申请日：2012-12-28
申请人： Kensuke OTA , Toshinori NUMATA , Masumi SAITOH , Chika TANAKA , Yusuke HIGASHI
发明人： Kensuke OTA , Toshinori NUMATA , Masumi SAITOH , Chika TANAKA , Yusuke HIGASHI
IPC分类号： H01L29/32
CPC分类号： H01L29/32 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78603 , H01L29/78696
摘要： A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.
摘要翻译：根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的掩埋绝缘层，形成在掩埋绝缘层上并且包括狭窄部分和比窄部分大的两个宽部分的半导体层并且分别连接到窄部分的一端和另一端，形成在窄部分的侧表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。直接在窄部下方的半导体衬底的杂质浓度高于窄部分的杂质浓度，并且直接在窄部下方的半导体衬底的杂质浓度高于直接在宽度以下的半导体衬底的杂质浓度一部分。

6. 发明申请

US20130175490A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130175490A1
公开(公告)日：2013-07-11
申请号：US13547645
申请日：2012-07-12
申请人： Haruka KUSAI , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
发明人： Haruka KUSAI , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
IPC分类号： H01L27/088 , H01L27/24 , H01L21/3205 , H01L21/768 , H01L21/265 , H01L21/02
CPC分类号： H01L27/088 , G11C16/04 , G11C16/10 , H01L21/02367 , H01L21/265 , H01L21/32051 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/685 , H01L29/788 , H01L29/792 , H01L29/82
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。结构和梁中的每一个包括沿垂直方向堆叠的半导体层。梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

7. 发明授权

US08467241B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08467241B2
公开(公告)日：2013-06-18
申请号：US13246996
申请日：2011-09-28
申请人： Jun Fujiki , Kiwamu Sakuma , Naoki Yasuda , Yukio Nakabayashi , Masumi Saitoh
发明人： Jun Fujiki , Kiwamu Sakuma , Naoki Yasuda , Yukio Nakabayashi , Masumi Saitoh
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/11568 , H01L29/4234
摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.
摘要翻译：在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置要写

8. 发明申请

US20120282743A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20120282743A1
公开(公告)日：2012-11-08
申请号：US13487295
申请日：2012-06-04
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/266 , H01L21/823437 , H01L21/823462 , H01L21/845 , H01L27/1211 , H01L29/66628 , H01L29/785
摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
摘要翻译：在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案，执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源在栅电极的两侧形成有引线区域。

9. 发明申请

US20120037994A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120037994A1
公开(公告)日：2012-02-16
申请号：US13283264
申请日：2011-10-27
申请人： Masumi SAITOH , Ken UCHIDA
发明人： Masumi SAITOH , Ken UCHIDA
IPC分类号： H01L27/092
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L29/0673 , H01L29/0676 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.
摘要翻译：提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管以及用于实现其的SMT引入制造方法。半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区，在其间插入通道区域。通道区域在与基板主平面垂直的方向上施加压缩应变。还公开了该装置的制造方法。

10. 发明授权

US07737486B2 Non-volatile semiconductor storage device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07737486B2
公开(公告)日：2010-06-15
申请号：US11859142
申请日：2007-09-21
申请人： Masumi Saitoh , Ken Uchida
发明人： Masumi Saitoh , Ken Uchida
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变，并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

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