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    • 3. 发明授权
    • Reconfigurable arithmetic unit and high-efficiency processor having the same
    • 可重构算术单元和具有相同功能的高效处理器
    • US08150903B2
    • 2012-04-03
    • US12136107
    • 2008-06-10
    • Yil Suk YangJung Hee SukChun Gi LyuhTae Moon RohJong Dae Kim
    • Yil Suk YangJung Hee SukChun Gi LyuhTae Moon RohJong Dae Kim
    • G06F7/57
    • G06F7/57G06F7/5324G06F7/5338
    • Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.
    • 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器,用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数,用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品,用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器(MUX),用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器(CPA),以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作,从而可以增加整个硬件的使用程度。
    • 10. 发明授权
    • Direct memory access controller and operating method thereof
    • 直接存储器存取控制器及其操作方法
    • US08799529B2
    • 2014-08-05
    • US13243470
    • 2011-09-23
    • Ik Jae ChunChun-Gi LyuhJung Hee SukSanghun YoonTae Moon Roh
    • Ik Jae ChunChun-Gi LyuhJung Hee SukSanghun YoonTae Moon Roh
    • G06F13/28
    • G06F13/28
    • Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels.
    • 公开了具有第一和第二DMA通道的直接存储器访问(DMA)控制器的操作方法。 操作方法包括:基于第一DMA通道的循环信息和传送信息来迭代地执行第一DMA通道的DMA传送操作; 基于所述第二DMA通道的循环信息和传送信息迭代地执行所述第二DMA通道的DMA传送操作; 重新配置第一和第二DMA通道的传送和循环信息; 并且基于第一和第二DMA通道的重新配置的传输和循环信息,再次执行迭代地执行第一DMA通道的DMA传送操作和迭代地执行第一DMA通道的DMA传送操作。