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1. 发明授权

US08448124B2 Post timing layout modification for performance 失效
标题翻译：发布时序布局修改的性能
公开(公告)号：US08448124B2
公开(公告)日：2013-05-21
申请号：US13236977
申请日：2011-09-20
申请人： Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
发明人： Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
摘要翻译：提供了一种用于性能的后期时序布局修改的机制。该机制基于路径级别的时序分析，选择性地应用布局修改。该机制仅将压力应用于处于设置关键路径的晶体管，而不对保持关键路径中的晶体管施加压力。该机制可以使用施加应力以提高晶体管在设置关键路径中的性能的方法，只要该应力不会改善保持关键路径中的相邻晶体管的性能即可。在一些情况下，该机制可以施加应力以改善设置关键路径中的晶体管的性能，同时降低保持关键路径中的晶体管的性能。

2. 发明授权

US08762919B2 Circuit macro placement using macro aspect ratio based on ports 失效
标题翻译：使用基于端口的宏宽高比的电路宏放置
公开(公告)号：US08762919B2
公开(公告)日：2014-06-24
申请号：US12949998
申请日：2010-11-19
申请人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
发明人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).
摘要翻译：通过基于由宏端口权重值，宏端口排序中的任何一个组成的标准修改可修改的轮廓形状宏的轮廓来操纵电子电路设计的固定轮廓形状和可修改轮廓形状的随机逻辑宏。宏观融合约束或宏观逻辑深度，并将结果宏放置在集成电路（芯片）的位置。

3. 发明授权

US08495551B2 Shaping ports in integrated circuit design 失效
标题翻译：整合端口集成电路设计
公开(公告)号：US08495551B2
公开(公告)日：2013-07-23
申请号：US12946179
申请日：2010-11-15
申请人： Joachim Keinert , Thomas Ludwig
发明人： Joachim Keinert , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports.
摘要翻译：提供了一种用于在集成电路中执行网络连接端口的详细路由的机制。为集成电路网的端口创建扩展端口区域，扩展端口区域被形成为保证对端口的路由访问。然后放置对应于网的线，并且修剪端口的扩展端口区域，从而确定将线连接到将线连接到端口不是必需的端口和可分配端口区域所需的基本端口区域。然后通过释放可分配端口区域来更新接线资源，使得可分配端口区域不再构成端口的一部分。

4. 发明授权

US08276105B2 Automatic positioning of gate array circuits in an integrated circuit design 有权
标题翻译：门阵列电路在集成电路设计中的自动定位
公开(公告)号：US08276105B2
公开(公告)日：2012-09-25
申请号：US12563021
申请日：2009-09-18
申请人： Joachim Keinert , Douglass T. Lamb , David W. Lewis , Shyam Ramji
发明人： Joachim Keinert , Douglass T. Lamb , David W. Lewis , Shyam Ramji
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits.
摘要翻译：一种用于在集成电路设计中定位门阵列电路的自动化方法和装置。初始集成电路设计包括位于其上的逻辑单元和门阵列填充电路。门阵列填充电路位于相邻逻辑单元之间的可用空间中，以便用最大门阵列填充电路填充可用空间。位于集成电路设计中的门阵列逻辑元件（例如可能需要通过电路设计的工程改变）被自动地定位在相邻逻辑单元之间，以便允许充分利用相邻逻辑之间剩余的任何空间电池通过门阵列填充电路。

5. 发明申请

US20110154283A1 Shaping Ports in Integrated Circuit Design 失效
标题翻译：整流端口集成电路设计
公开(公告)号：US20110154283A1
公开(公告)日：2011-06-23
申请号：US12946179
申请日：2010-11-15
申请人： Joachim Keinert , Thomas Ludwig
发明人： Joachim Keinert , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports.
摘要翻译：提供了一种用于在集成电路中执行网络连接端口的详细路由的机制。为集成电路网的端口创建扩展端口区域，扩展端口区域被形成为保证对端口的路由访问。然后放置对应于网的线，并且修剪端口的扩展端口区域，从而确定将线连接到将线连接到端口不是必需的端口和可分配端口区域所需的基本端口区域。然后通过释放可分配端口区域来更新接线资源，使得可分配端口区域不再构成端口的一部分。

6. 发明授权

US6094812A Dishing avoidance in wide soft metal wires 有权
标题翻译：在宽软金属线中避免避免
公开(公告)号：US6094812A
公开(公告)日：2000-08-01
申请号：US163149
申请日：1998-09-29
申请人： George English , Joachim Keinert , Oliver Rettig
发明人： George English , Joachim Keinert , Oliver Rettig
IPC分类号： H01L21/768 , H01K3/10
CPC分类号： G06F17/5068 , H01L21/7684 , G06F2217/12 , Y02P90/265 , Y10T29/49121 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing semiconductor circuits or electronic packages is provided. The step of splitting up wide metal areas into metal stripes is included into the physical design step of such devices. This method does not increase the data complexity significantly and guarantees correctness of the design. Furthermore, the method allows to solve the dishing problem that is inherent to copper wiring technologies.
摘要翻译：提供一种制造半导体电路或电子封装的方法。将宽金属区域分割成金属条纹的步骤包括在这种装置的物理设计步骤中。该方法不会显着提高数据复杂度，保证设计的正确性。此外，该方法允许解决铜布线技术固有的凹陷问题。

7. 发明申请

US20120123725A1 PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US20120123725A1
公开(公告)日：2012-05-17
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅里叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

8. 发明授权

US08122400B2 Logic difference synthesis 有权
标题翻译：逻辑差分合成
公开(公告)号：US08122400B2
公开(公告)日：2012-02-21
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

9. 发明申请

US20110113395A1 Method, Electronic Design Automation Tool, Computer Program Product, and Data Processing Program for Creating a Layout for Design Representation of an Electronic Circuit and Corresponding Port for an Electronic Circuit 失效
标题翻译：方法，电子设计自动化工具，计算机程序产品和数据处理程序，用于创建用于电子电路的电子电路和相应端口的设计表示的布局
公开(公告)号：US20110113395A1
公开(公告)日：2011-05-12
申请号：US12861087
申请日：2010-08-23
申请人： Joachim Keinert , Thomas Ludwig
发明人： Joachim Keinert , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5077 , G06F2217/84
摘要： A method for creating a layout for design representation of an electronic circuit with at least one port. The method includes segmenting the at least one port in the design representation into different regions, classifying the different regions of the at least one port according to timing and/or electronic and/or layout characteristics, assigning a priority for each classified region of the at least one port according to rules based on the timing and/or electronic and/or layout characteristics, and routing the design representation by accessing at least one of the classified regions of the port according to an order of the assigned priorities.
摘要翻译：一种用于创建具有至少一个端口的电子电路的设计表示的布局的方法。该方法包括将设计表示中的至少一个端口分段成不同的区域，根据时间和/或电子和/或布局特征对至少一个端口的不同区域进行分类，为每个分类区域的每个分类区域分配优先级根据所述定时和/或电子和/或布局特性的规则，至少一个端口，并且根据所分配的优先级的顺序，通过访问所述端口的分类区域中的至少一个来路由设计表示。

10. 发明申请

US20110004857A1 LOGIC DIFFERENCE SYNTHESIS 有权
标题翻译：逻辑差异综合
公开(公告)号：US20110004857A1
公开(公告)日：2011-01-06
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

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