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1. 发明授权

US09263114B2 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US09263114B2
公开(公告)日：2016-02-16
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00 , G11C11/15 , G11C11/56
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

2. 发明授权

US09177641B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09177641B2
公开(公告)日：2015-11-03
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

3. 发明授权

US08953917B2 Low bend loss optical fiber 有权
标题翻译：低弯曲损耗光纤
公开(公告)号：US08953917B2
公开(公告)日：2015-02-10
申请号：US13680641
申请日：2012-11-19
申请人： George Edward Berkey , Dana Craig Bookbinder , Steven Bruce Dawes , Ming-Jun Li , Pushkar Tandon , Ji Wang
发明人： George Edward Berkey , Dana Craig Bookbinder , Steven Bruce Dawes , Ming-Jun Li , Pushkar Tandon , Ji Wang
IPC分类号： G02B6/036 , G02B6/028
CPC分类号： G02B6/028 , G02B6/0286 , G02B6/03627 , G02B6/03638 , G02B6/0365
摘要： According to some embodiments a single mode fiber includes: a germania doped central core region having outer radius r1 and relative refractive index Δ1; and a cladding region comprising (i) a first inner cladding region having an outer radius r2>6 microns and relative refractive index Δ2 and 0.3≦r1/r2≦0.85; and (ii) a second inner cladding region having an outer radius r3>9 microns and comprising a minimum relative refractive index Δ3, wherein said second inner cladding region has at least one region with a relative refractive index delta that becomes more negative with increasing radius; and (iii) an outer cladding region surrounding the second inner cladding region and comprising relative refractive index Δ4, wherein Δ1>Δ2>Δ3, Δ3
摘要翻译：根据一些实施例，单模光纤包括：具有外半径r1和相对折射率＆Dgr; 1的掺杂锗的中心芯区域; 包括区域，其包括（i）具有外半径r2> 6微米的第一内包层区域和相对折射率＆lt; Dgr; 2和0.3＆amp; nlE; r1 / r2＆nlE; 0.85; 和（ii）外半径r3> 9微米并且包括最小相对折射率＆lt; Dgr; 3的第二内包层区域，其中所述第二内包层区域具有至少一个相对折射率Δδ的区域变得更为负，半径增加 4，一种包围第二内包层区域的外包层区，包括相对折射率＆Dgr; 4，其中＆Dgr; 1＆Dgr; 2＆Dgr; 3，＆Dgr; 3＆

4. 发明授权

US08904828B2 Methods for forming cladding portions of optical fiber preform assemblies 有权
标题翻译：用于形成光纤预制组件的包层部分的方法
公开(公告)号：US08904828B2
公开(公告)日：2014-12-09
申请号：US12603960
申请日：2009-10-22
申请人： Steven Bruce Dawes , Lisa A. Hogue , Douglas H. Jennings , Zhiqiang Shi , Christopher Scott Thomas , Ji Wang
发明人： Steven Bruce Dawes , Lisa A. Hogue , Douglas H. Jennings , Zhiqiang Shi , Christopher Scott Thomas , Ji Wang
IPC分类号： C03B37/012
CPC分类号： C03B37/01282
摘要： A method of forming a cladding portion of an optical fiber preform assembly includes positioning a glass core cane in a mold cavity and loading the mold cavity with silica glass soot. The silica glass soot is compressed in an axial direction as the vibratory energy is applied to the mold body to form a soot compact around the glass core cane, wherein the soot compact is the cladding portion of an optical fiber preform assembly and the glass core cane is a core portion of the optical fiber preform assembly.
摘要翻译：形成光纤预制组件的包层部分的方法包括将玻璃芯棒定位在模腔中并且用石英玻璃烟灰装载模腔。随着振动能量施加到模具体上，二氧化硅玻璃烟灰在轴向被压缩以在玻璃芯棒周围形成烟炱压块，其中烟炱压实体是光纤预制组件的包层部分，并且玻璃芯棒是光纤预制组件的核心部分。

5. 发明申请

US20140286082A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286082A1
公开(公告)日：2014-09-25
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

6. 发明授权

US08610458B2 Impedance control circuit and semiconductor device including the same 有权
标题翻译：阻抗控制电路和包括其的半导体器件
公开(公告)号：US08610458B2
公开(公告)日：2013-12-17
申请号：US13446527
申请日：2012-04-13
申请人： Ji-Wang Lee
发明人： Ji-Wang Lee
IPC分类号： H03K19/003 , H03L5/00
CPC分类号： H03K19/018571 , H03K19/0005 , H03K19/018585
摘要： An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.
摘要翻译：阻抗控制电路包括：第一阻抗单元，被配置为使用由阻抗控制代码确定的阻抗值来终止阻抗节点;第二阻抗单元，被配置为使用由阻抗控制电压确定的阻抗值来终止阻抗节点比较电路，被配置为比较阻抗节点的电压电平和参考电压的电压电平，生成表示阻抗节点处的电压是否大于参考电压的上/下信号，并产生阻抗控制电压其具有对应于阻抗节点处的电压与参考电压之间的差的电压电平，以及配置为响应于上/下信号增加或减少阻抗控制代码的值的计数器单元。

7. 发明申请

US20130071114A1 FEW MODE OPTICAL FIBERS FOR MODE DIVISION MULTIPLEXING 有权
标题翻译：用于模式分割多路复用的模式光纤
公开(公告)号：US20130071114A1
公开(公告)日：2013-03-21
申请号：US13420037
申请日：2012-03-14
申请人： Scott Robertson Bickham , Ming-Jun Li , Daniel Aloysius Nolan , Ji Wang
发明人： Scott Robertson Bickham , Ming-Jun Li , Daniel Aloysius Nolan , Ji Wang
IPC分类号： G02B6/028 , H04J14/04
CPC分类号： G02B6/0288 , G02B6/02019 , G02B6/02023 , G02B6/03627 , G02B6/0365 , H04J14/04
摘要： A few mode optical fiber suitable for use in a mode division multiplexing (MDM) optical transmission system is disclosed. The optical fiber has a graded-index core with a radius R1 in the range from 8 μm to 14 μm, an alpha value greater than or equal to about 2.3 and less than about 2.7 at a wavelength of 1550 nm, and a maximum relative refractive index Δ1MAX from about 0.3% to about 0.6% relative to the cladding. The optical fiber also has an effective area greater than about 90 μm2 and less than about 160 μm2. The core and cladding support only the LP01 and LP11 modes at wavelengths greater than 1500 nm. The cladding has a maximum relative refractive index Δ4MAX such that Δ1MAX>Δ4MAX, and the differential group delay between the LP01 and LP11 modes is less than about 0.5 ns/km at a wavelength of 1550 nm.
摘要翻译：公开了适用于模分多路复用（MDM）光传输系统的几种模式光纤。光纤具有半径R1在8μm至14μm范围内的梯度折射率芯，在1550nm波长处大于或等于约2.3且小于约2.7的α值，以及最大相对折射率指数＆Dgr; 1MAX，相对于包层为约0.3％至约0.6％。该光纤还具有大于约90μm2且小于约160μm2的有效面积。芯和包层只支持波长大于1500 nm的LP01和LP11模式。包层具有最大相对折射率＆Dgr; 4MAX，使得＆Dgr; 1MAX>＆Dgr; 4MAX，并且LP01和LP11模式之间的差分群延迟在1550nm的波长处小于约0.5ns / km。

8. 发明授权

US08373456B2 Domain crossing circuit of a semiconductor memory apparatus 有权
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08373456B2
公开(公告)日：2013-02-12
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

9. 发明申请

US20120134762A1 MOVING BEAM TYPE MACHINE TOOL 审中-公开
标题翻译：移动梁式机床
公开(公告)号：US20120134762A1
公开(公告)日：2012-05-31
申请号：US13044910
申请日：2011-03-10
申请人： Jen-Ji Wang , En-Sheng Chang , Chih-Ming Chen
发明人： Jen-Ji Wang , En-Sheng Chang , Chih-Ming Chen
IPC分类号： B23C1/06 , B23C1/14
CPC分类号： B23Q11/0028 , Y10T29/5114 , Y10T409/305712 , Y10T409/307672 , Y10T409/308288
摘要： A moving beam type machine tool is disclosed, having a dynamic phase balancing weight set and a spindle saddle. The spindle saddle has at least one X-axis location feedback device. When the spindle saddle along the X-axis traverse, the at least one X-axis location feedback device is able to locate the spindle saddle and inform a controlling unit. The controlling unit changes the output pressure of the dynamic phase balancing weight set depending on the location of the spindle saddle, so that a crossbeam is able to maintain in a balancing state. The moving beam type machine tool is able to increase accurate, sensitivity of pressure response, withstanding weight and balancing state.
摘要翻译：公开了一种具有动态相位平衡重量组和主轴鞍座的移动梁式机床。主轴座具有至少一个X轴定位反馈装置。当主轴沿X轴移动时，至少一个X轴位置反馈装置能够定位主轴鞍座并通知控制单元。控制单元根据主轴鞍座的位置改变动态相位平衡重量的输出压力，使得横梁能够保持平衡状态。移动梁式机床能够提高压力响应的精度，灵敏度，承受重量和平衡状态。

10. 发明授权

US08171189B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US08171189B2
公开(公告)日：2012-05-01
申请号：US12648524
申请日：2009-12-29
申请人： Ji Wang Lee , Hee Woong Song , Tae Jin Hwang
发明人： Ji Wang Lee , Hee Woong Song , Tae Jin Hwang
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4072
摘要： A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.
摘要翻译：半导体装置包括时钟输入缓冲器，异步数据输入缓冲器和同步数据输入缓冲器。时钟输入缓冲器配置为缓冲外部时钟以产生内部时钟。异步数据输入缓冲器被配置为缓冲通过数据焊盘输入的数据并输出缓冲的数据。同步数据输入缓冲器被配置为与内部时钟同步以缓冲缓冲的数据。半导体装置被布置成使得用于将内部时钟传送到同步数据输入缓冲器的线的长度和用于将缓冲数据传送到同步数据输入缓冲器的线的长度基本上彼此相等。

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