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1. 发明授权

US08504960B2 Method and system for high speed and low memory footprint static timing analysis 有权
标题翻译：高速和低内存占用静态时序分析方法和系统
公开(公告)号：US08504960B2
公开(公告)日：2013-08-06
申请号：US12451308
申请日：2008-05-16
申请人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
发明人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031
摘要： The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be nm on inexpensive, off-the-shelf hardware.
摘要翻译：本发明提供了一种用于在SoC（片上系统）设计上进行静态时序分析的方法和系统。本发明解决了设计时序分析的长期问题，即分析设计多线程的能力。本发明提供了将设计切片成级别，将每个级别进一步分解成门，以及门的多线程处理，使得大规模设计分析的解决方案比当前方法快得多。此外，本发明提供了在RAM中只有一个级别。一旦计算了该级别的到达时间，数据将立即保存到磁盘。由于内存占用空间与设计的尺寸是亚线性的，因此整个系统级芯片设计可以在廉价的现成硬件上运行。

2. 发明申请

US20100131911A1 Method and system for High Speed and Low Memory Footprint Static Timing Analysis 有权
标题翻译：高速和低内存占位静态时序分析方法与系统
公开(公告)号：US20100131911A1
公开(公告)日：2010-05-27
申请号：US12451308
申请日：2008-05-16
申请人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
发明人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031
摘要： The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be nm on inexpensive, off-the-shelf hardware.
摘要翻译：本发明提供了一种用于在SoC（片上系统）设计上进行静态时序分析的方法和系统。本发明解决了设计时序分析的长期问题，即分析设计多线程的能力。本发明提供了将设计切片成级别，将每个级别进一步分解成门，以及门的多线程处理，使得大规模设计分析的解决方案比当前方法快得多。此外，本发明提供了在RAM中只有一个级别。一旦计算了该级别的到达时间，数据将立即保存到磁盘。由于内存占用空间与设计的尺寸是亚线性的，因此整个系统级芯片设计可以在廉价的现成硬件上运行。

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