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1. 发明授权

US4575821A Low power, high speed random access memory circuit 失效
标题翻译：低功耗，高速随机存取电路
公开(公告)号：US4575821A
公开(公告)日：1986-03-11
申请号：US493093
申请日：1983-05-09
申请人： Richard C. Eden , George R. Kaelin
发明人： Richard C. Eden , George R. Kaelin
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , G11C7/00 , G11C11/34
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419
摘要： A random access memory circuit for use with positive and negative supply voltages, a read enable line, an output line, and write "1" and "0" lines includes first, second, third, and fourth level shifting diodes. A first input isolation diode is connected between the write "1" line and the first level shifting diode. A second input isolation diode is connected between the write "0" line and the cathode of the third level shifting diode. The drain of a first write FET is connected to the anode of the third diode, the source is connected to the read enable line, and the gate is connected to the cathode of the second level shifting diode. A second write FET has its drain connected to the anode of the first level shifting diode, its source connected to the read enable line, and its gate connected to the cathode of the fourth diode. An output buffer FET is connected by its source to the read enable line, by its gate to the cathode of the fourth diode. An output isolation diode is connected between the drain of the output buffer FET and the output line.
摘要翻译：用于正电源电压和负电源电压的随机存取存储器电路，读使能线，输出线和写“1”和“0”线包括第一，第二，第三和第四电平移位二极管。第一输入隔离二极管连接在写“1”线和第一电平移位二极管之间。第二输入隔离二极管连接在写“0”线和第三电平转换二极管的阴极之间。第一写FET的漏极连接到第三二极管的阳极，源极连接到读使能线，栅极连接到第二电平移位二极管的阴极。第二写FET的漏极连接到第一电平移位二极管的阳极，其源极连接到读使能线，其栅极连接到第四二极管的阴极。输出缓冲FET由其源极连接到读使能线，其栅极连接到第四二极管的阴极。输出隔离二极管连接在输出缓冲FET的漏极和输出线之间。

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