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1. 发明授权

US08878712B2 Flash ADC shuffling 有权
标题翻译：闪存ADC混洗
公开(公告)号：US08878712B2
公开(公告)日：2014-11-04
申请号：US13829257
申请日：2013-03-14
申请人： John Cullinane , Frederick Carnegie Thompson
发明人： John Cullinane , Frederick Carnegie Thompson
IPC分类号： H03M1/36 , H03M1/34
CPC分类号： H03M1/0673 , H03M1/145 , H03M1/365
摘要： A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.
摘要翻译：闪存ADC电路可以包括提供参考信号的参考梯形图和多个比较器，每个比较器基于一对输入信号与一对参考信号的比较来提供输出。至少一对比较器可以在每个比较器处以不同的参考信号取向接收相同的一对参考信号。闪存ADC可以包括用于在一对比较器之间交换一对参考信号的开关网络。

2. 发明申请

US20110069840A1 DIGITAL TO ANALOG CONVERTER SYSTEM AND METHOD WITH MULTI-LEVEL SCRAMBLING 有权
标题翻译：数字到模拟转换器系统和方法与多级SCRAMBLING
公开(公告)号：US20110069840A1
公开(公告)日：2011-03-24
申请号：US12624413
申请日：2009-11-24
申请人： John Jude O'Donnell , Frederick Carnegie Thompson
发明人： John Jude O'Donnell , Frederick Carnegie Thompson
IPC分类号： H04L9/00
CPC分类号： H03M1/067 , H03M1/74 , H03M3/502 , H04L25/03866
摘要： Tri-level scrambling in a digital to analog converter system is achieved by, in response to a tri-level binary code input, disabling a negative data directed scrambler circuit when the input code is in the positive cycle portion, disabling a positive data directed scrambler circuit when the input code is in the negative cycle portion and disabling both scrambler circuits upon a zero input code for reducing low level distortion due to a reversal of current during crossover between those cycles.
摘要翻译：数字到模拟转换器系统中的三电平扰频通过响应于三电平二进制码输入来实现，当输入码处于正周期部分时禁用负数据定向扰频电路，禁用正数据定向扰频器当输入代码处于负周期部分时，并且在零输入代码上禁用两个扰频器电路，以便在这些周期之间的交叉期间由于电流反转而导致的低电平失真。

3. 发明授权

US08786483B1 Use of a DLL to optimize an ADC performance 有权
标题翻译：使用DLL来优化ADC性能
公开(公告)号：US08786483B1
公开(公告)日：2014-07-22
申请号：US13830382
申请日：2013-03-14
申请人： Frederick Carnegie Thompson , Barry Stakely
发明人： Frederick Carnegie Thompson , Barry Stakely
IPC分类号： H03M1/38
CPC分类号： H03M1/0836 , H03M1/125 , H03M1/462
摘要： Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.
摘要翻译：本发明的实施例可以提供用于校正与异步逐次逼近寄存器（SAR）模数转换器（ADC）中的过程，电压和温度效应相关联的定时误差的改进的装置和方法。 SAR ADC可以包括定时器，其包括可编程定时电路，其可以确保SAR ADC的不同部件根据定时方案工作。定时电路的工作可能随过程，电压和温度而变化，这可能不利地影响SAR ADC的定时/精度。 ADC可以包括与SAR ADC相同的集成电路上提供的参考电路，该ADC可以为定时电路提供定时参考。如果参考电路指示定时电路的运行速度比理想速度更快或更慢，则定时电路内的定时值可被修改以补偿这种变化。

4. 发明授权

US07994957B2 Current steering digital-to-analog converter 有权
标题翻译：电流转向数模转换器
公开(公告)号：US07994957B2
公开(公告)日：2011-08-09
申请号：US12560602
申请日：2009-09-16
申请人： John Jude O'Donnell , Frederick Carnegie Thompson
发明人： John Jude O'Donnell , Frederick Carnegie Thompson
IPC分类号： H03M1/66
CPC分类号： H03M1/0836 , H03M1/66
摘要： A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal.
摘要翻译：数模转换器（DAC）模块接收具有第一数据速率并与第一频率相关联的输入数字信号，DAC模块还接收具有高于第一频率的第二频率的同步信号。 DAC模块包括上采样电路，用于产生具有与零值交替的输入数字信号的位值的第一数字信号，第一数字信号具有高于第一数据速率的数据速率; 延迟电路，用于将第一数字信号延迟一段时间以产生第二数字信号; 第一DAC单元，用于基于第一数字信号产生第一模拟信号，第一DAC单元由同步信号同步; 第二DAC单元，用于基于所述第二数字信号产生第二模拟信号，所述第二DAC单元由所述同步信号同步; 以及加法器，用于对第一和第二模拟信号求和并产生第三模拟信号。

5. 发明授权

US09647620B2 Electronic device and integrated circuit comprising a gain control module and method therefor 有权
公开(公告)号：US09647620B2
公开(公告)日：2017-05-09
申请号：US12688909
申请日：2010-01-17
申请人： Patrick Alan O'Connell , Niall McDermott , Frederick Carnegie Thompson
发明人： Patrick Alan O'Connell , Niall McDermott , Frederick Carnegie Thompson
IPC分类号： H03G3/00
CPC分类号： H03G3/002 , H03G3/001
摘要： A method for controlling a gain applied to an audio signal. The method comprises applying a gain step to a gain setting at defined time intervals, and upon detection of at least one zero crossing point within the audio signal, applying the gain setting to a gain control signal for controlling the gain applied to the audio signal.

6. 发明申请

US20140266842A1 BIT ERROR RATE TIMER FOR A DYNAMIC LATCH 有权
标题翻译：用于动态锁定的位错误率定时器
公开(公告)号：US20140266842A1
公开(公告)日：2014-09-18
申请号：US13839972
申请日：2013-03-15
申请人： Frederick Carnegie THOMPSON , John CULLINANE
发明人： Frederick Carnegie THOMPSON , John CULLINANE
IPC分类号： H03M1/14
CPC分类号： H03M1/145 , H03M1/36 , H03M1/46
摘要： A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.
摘要翻译： A转换器系统，包括对输入信号的第一部分进行数字化的第一转换器，第一转换器包括比较器，具有模拟第一转换器中的比较器的电路结构的电路结构的定时器，定时器接收输入信号，其指示比较器中的操作开始;第二转换器，响应于来自定时器的输出，数字化从第一部分剩余的输入信号的第二部分;以及组合器，具有从第一数字化生成数字代码的输入，第二部分。

7. 发明授权

US08085177B2 Digital to analog converter system and method with multi-level scrambling 有权
标题翻译：数模转换器系统及方法具有多级扰频
公开(公告)号：US08085177B2
公开(公告)日：2011-12-27
申请号：US12624413
申请日：2009-11-24
申请人： John Jude O'Donnell , Frederick Carnegie Thompson
发明人： John Jude O'Donnell , Frederick Carnegie Thompson
IPC分类号： H03M1/66
CPC分类号： H03M1/067 , H03M1/74 , H03M3/502 , H04L25/03866
摘要： Tri-level scrambling in a digital to analog converter system is achieved by, in response to a tri-level binary code input, disabling a negative data directed scrambler circuit when the input code is in the positive cycle portion, disabling a positive data directed scrambler circuit when the input code is in the negative cycle portion and disabling both scrambler circuits upon a zero input code for reducing low level distortion due to a reversal of current during crossover between those cycles.
摘要翻译：数字到模拟转换器系统中的三电平扰频通过响应于三电平二进制码输入来实现，当输入码处于正周期部分时禁用负数据定向扰频电路，禁用正数据定向扰频器当输入代码处于负周期部分时，并且在零输入代码上禁用两个扰频器电路，以便在这些周期之间的交叉期间由于电流反转而导致的低电平失真。

8. 发明申请

US20110176693A1 ELECTRONIC DEVICE AND INTEGRATED CIRCUIT COMPRISING A GAIN CONTROL MODULE AND METHOD THEREFOR 有权
标题翻译：包含增益控制模块的电子设备和集成电路及其方法
公开(公告)号：US20110176693A1
公开(公告)日：2011-07-21
申请号：US12688909
申请日：2010-01-17
申请人： Patrick Alan O'Connell , Niall McDermott , Frederick Carnegie Thompson
发明人： Patrick Alan O'Connell , Niall McDermott , Frederick Carnegie Thompson
IPC分类号： H03F99/00
CPC分类号： H03G3/002 , H03G3/001
摘要： A method for controlling a gain applied to an audio signal. The method comprises applying a gain step to a gain setting at defined time intervals, and upon detection of at least one zero crossing point within the audio signal, applying the gain setting to a gain control signal for controlling the gain applied to the audio signal.
摘要翻译：一种用于控制应用于音频信号的增益的方法。所述方法包括以规定的时间间隔对增益设置应用增益步长，并且在检测到音频信号中的至少一个过零点之后，将增益设置应用于增益控制信号，以控制施加到音频信号的增益。

9. 发明申请

US20110007912A1 DOUBLE INTEGRAL METHOD OF POWERING UP OR DOWN A SPEAKER 审中-公开
标题翻译：提升或降低扬声器的双重整合方法
公开(公告)号：US20110007912A1
公开(公告)日：2011-01-13
申请号：US12498745
申请日：2009-07-07
申请人： Frederick Carnegie Thompson
发明人： Frederick Carnegie Thompson
IPC分类号： H04B15/00
CPC分类号： H03F1/305 , H03F2200/03 , H03G3/348 , H04R3/007
摘要： An audio subsystem having a waveform generation circuit that generates a power-up signal for controlling an electric signal used to drive a speaker during a power-up period in which the power-up signal has a positive second derivative during a first sub-period of the power-up period and has a negative second derivative during a second sub-period of the power-up period. The first sub-period spans at least one-fourth of the power-up period, and the second sub-period spans at least one-fourth of the power-up period.
摘要翻译：一种音频子系统，具有波形发生电路，该波形发生电路在上电期间产生用于控制用于驱动扬声器的电信号的上电信号，在上电期间，上电信号在第一子周期期间具有正二次导数上电期间，在上电期间的第二个子期间为负二次导数。第一个分期至少是上电时间的四分之一，第二个分期至少是上电周期的四分之一。

10. 发明申请

US20140266839A1 FLASH ADC SHUFFLING 有权
标题翻译：闪存ADC SHUFFLING
公开(公告)号：US20140266839A1
公开(公告)日：2014-09-18
申请号：US13829257
申请日：2013-03-14
申请人： John CULLINANE , Frederick Carnegie THOMPSON
发明人： John CULLINANE , Frederick Carnegie THOMPSON
IPC分类号： H03M1/34
CPC分类号： H03M1/0673 , H03M1/145 , H03M1/365
摘要： A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.
摘要翻译：闪存ADC电路可以包括提供参考信号的参考梯形图和多个比较器，每个比较器基于一对输入信号与一对参考信号的比较来提供输出。至少一对比较器可以在每个比较器处以不同的参考信号取向接收相同的一对参考信号。闪存ADC可以包括用于在一对比较器之间交换一对参考信号的开关网络。

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