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1. 发明申请

US20050111285A1 Arrangement with a memory for storing data 有权
标题翻译：用于存储数据的存储器的布置
公开(公告)号：US20050111285A1
公开(公告)日：2005-05-26
申请号：US10997321
申请日：2004-11-24
申请人： Ernst Kock , Walter Mischo
发明人： Ernst Kock , Walter Mischo
IPC分类号： G11C8/00 , G11C29/00
CPC分类号： G11C29/846
摘要： The document describes an arrangement having a first memory for storing data, switching devices which stipulate whether access to the first memory involves output of the data stored in the first memory or other data, and a second memory for storing the other data. The arrangement described is distinguished in that it contains a third memory (103, 203, 310), which is addressed by the address (A) which is used to access the first memory or by a portion (AH) of this address and contains information about which data in the first memory are to be replaced with other data.
摘要翻译：该文献描述了具有用于存储数据的第一存储器，规定对第一存储器的访问是否涉及存储在第一存储器中的数据的输出或其他数据的布置，以及用于存储其他数据的第二存储器。所描述的布置的区别在于它包含第三存储器（103,203,310），其由用于访问第一存储器或由该地址的一部分（AH）的地址（A）寻址，并且包含信息关于第一存储器中的哪些数据将被其他数据替换。

2. 发明申请

US20050157586A1 Arrangement comprising a memory device and a program-controlled unit 有权
标题翻译：布置包括存储器件和程序控制单元
公开(公告)号：US20050157586A1
公开(公告)日：2005-07-21
申请号：US11018327
申请日：2004-12-21
申请人： Ernst Kock , Frank Hellwig
发明人： Ernst Kock , Frank Hellwig
IPC分类号： G06F13/12 , G11C7/22 , G11C8/00 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： An arrangement comprises a memory device for storing data, and a program-controlled unit with a memory interface for reading data out of the memory device. The memory device is supplied with a first clock signal and transmits the data at the rate of a second clock signal, and the second clock signal to the memory interface when the memory interface performs a read access. The first clock signal is also supplied to the memory interface which generates from this signal a third clock signal which has the same frequency as the first and second clock signal but a predetermined phase shift with respect to the second clock signal. The memory interface accepts the data with the rising and/or falling edges of the third clock signal or the inverted third clock signal, and the third clock signal is also used as clock signal by other components of the memory interface.
摘要翻译：一种装置包括用于存储数据的存储装置，以及具有用于从存储装置读出数据的存储器接口的程序控制单元。当存储器接口执行读取访问时，存储器件被提供有第一时钟信号并以第二时钟信号的速率传输数据，并且将第二时钟信号发送到存储器接口。第一时钟信号也被提供给从该信号产生具有与第一和第二时钟信号相同频率但相对于第二时钟信号的预定相移的第三时钟信号的存储器接口。存储器接口接收具有第三时钟信号或反相第三时钟信号的上升沿和/或下降沿的数据，并且第三时钟信号也被存储器接口的其他部件用作时钟信号。

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