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1. 发明授权

US5613071A Method and apparatus for providing remote memory access in a distributed memory multiprocessor system 失效
标题翻译：用于在分布式存储器多处理器系统中提供远程存储器访问的方法和装置
公开(公告)号：US5613071A
公开(公告)日：1997-03-18
申请号：US502071
申请日：1995-07-14
申请人： Linda J. Rankin , Joseph Bonasera , Nitin Y. Borkar , Linda C. Ernst , Suvansh K. Kapur , Daniel A. Manseau , Frank Verhoorn
发明人： Linda J. Rankin , Joseph Bonasera , Nitin Y. Borkar , Linda C. Ernst , Suvansh K. Kapur , Daniel A. Manseau , Frank Verhoorn
IPC分类号： G06F12/02 , G06F15/173
CPC分类号： G06F15/17381 , G06F12/0284
摘要： A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.
摘要翻译：公开了一种大规模并行的数据处理系统。该数据处理系统包括多个节点，每个节点具有至少一个处理器，用于存储数据的存储器，将处理器耦合到存储器的处理器总线以及耦合到处理器总线的远程存储器访问控制器。远程存储器访问控制器检测和排队处理器对远程存储器的请求，将处理器请求处理和打包成请求包，通过与该节点对应的路由器将请求包转发到网络，接收并排队从网络接收的请求包，从请求分组恢复存储器请求，根据请求操纵本地存储器，生成可接受的适当的响应分组，并将响应分组转发到请求节点。

2. 发明授权

US06629219B1 Method and apparatus for providing highly programmable memory mapping and improved interleaving 失效
标题翻译：用于提供高可编程存储器映射和改进的交织的方法和装置
公开(公告)号：US06629219B1
公开(公告)日：2003-09-30
申请号：US09541448
申请日：2000-03-31
申请人： Daniel A. Manseau
发明人： Daniel A. Manseau
IPC分类号： G06F1200
CPC分类号： G06F12/0607 , G06F12/0653
摘要： A method and apparatus for providing highly programmable memory mapping and improved interleaving includes a system address chip that maps a received memory transaction address to an intermediate address for accessing a memory array having at least one individually addressable memory row. During the translation the memory array is logically partitioned into a plurality of individually addressable memory blocks such that each of said memory blocks are interleavingly accessible independent of how said memory array is populated. The apparatus includes logic to generate at least a portion of the intermediate address by combining selected bits of the transaction address with selected bits of a programmed block address based in part upon the received transaction address.
摘要翻译：用于提供高度可编程存储器映射和改进的交织的方法和装置包括将接收到的存储器事务地址映射到用于访问具有至少一个单独可寻址存储器行的存储器阵列的中间地址的系统地址芯片。在翻译期间，存储器阵列在逻辑上被划分成多个可单独寻址的存储器块，使得每个所述存储器块都可交替地访问，而不管如何填充存储器阵列。该装置包括通过部分地基于所接收的交易地址将交易地址的所选位与已编程块地址的选定位组合来生成中间地址的至少一部分的逻辑。

3. 发明授权

US4464657A Modular waveform generator for plasma display panels 失效
标题翻译：等离子显示面板的模块化波形发生器
公开(公告)号：US4464657A
公开(公告)日：1984-08-07
申请号：US273092
申请日：1981-06-12
申请人： Michael J. Marentic , Daniel A. Manseau
发明人： Michael J. Marentic , Daniel A. Manseau
IPC分类号： G09G3/28 , G09G3/288
CPC分类号： G09G3/296 , G09G3/2927 , G09G3/2944 , G09G2310/0232 , G09G2320/0626 , G09G3/297
摘要： Complex waveforms used to control a plasma panel are formed as sequences of common elemental waveform modules. These modules are combined in various orders into strings capable of performing various functions on the plasma panel. Large scale parallel addressing is accomplished by forming a string of several sustain modules, followed by a write or erase module.
摘要翻译：用于控制等离子面板的复杂波形形成为公共元素波形模块的序列。这些模块以各种顺序组合成能够在等离子体面板上执行各种功能的串。大规模并行寻址是通过形成几个维持模块的串，后跟写或擦除模块完成的。

4. 发明授权

US07701973B2 Processing receive protocol data units 失效
标题翻译：处理接收协议数据单元
公开(公告)号：US07701973B2
公开(公告)日：2010-04-20
申请号：US10879770
申请日：2004-06-28
申请人： Nicholas A. Colman , Ramesh S. Krishnan , Anshuman Thakur , Robert Cone , Daniel A. Manseau
发明人： Nicholas A. Colman , Ramesh S. Krishnan , Anshuman Thakur , Robert Cone , Daniel A. Manseau
IPC分类号： H04J3/16
CPC分类号： H04L29/06 , H04L69/16 , H04L69/22
摘要： Provided are techniques for processing a data segment by stripping a header from a transport layer segment, performing protocol data unit detection to determine data for a protocol segment that is part of the transport layer segment data, and performing marker validation and stripping.
摘要翻译：提供了通过从传输层段剥离报头来处理数据段的技术，执行协议数据单元检测以确定作为传输层段数据的一部分的协议段的数据，以及执行标记验证和剥离。

5. 发明授权

US07475167B2 Offloading data path functions 有权
标题翻译：卸载数据路径功能
公开(公告)号：US07475167B2
公开(公告)日：2009-01-06
申请号：US11106799
申请日：2005-04-15
申请人： Mark W. Wunderlich , Hemal V. Shah , Anshuman Thakur , Daniel A. Manseau
发明人： Mark W. Wunderlich , Hemal V. Shah , Anshuman Thakur , Daniel A. Manseau
IPC分类号： G06F15/16 , G06F3/00 , G06F12/00 , G06F9/34 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L67/1097 , H04L69/12 , H04L2212/00
摘要： Input/Output (I/O) protocol operations such as iSCSI protocol operations may be selectively offloaded to an I/O protocol offload device, or retained by a host driver software. In one embodiment, iSCSI data transfer functions are offloaded to an offload device while session and connection establishing and maintenance operations are retained by host driver software. Other features are described and claimed.
摘要翻译：输入/输出（I / O）协议操作（如iSCSI协议操作）可以选择性地卸载到I / O协议卸载设备，或由主机驱动程序软件保留。在一个实施例中，iSCSI数据传输功能被卸载到卸载设备，而主机驱动程序软件保留会话和连接建立和维护操作。描述和要求保护其他特征。

6. 发明授权

US06772300B1 Method and apparatus for managing out of order memory transactions 失效
标题翻译：用于管理不合格存储器事务的方法和装置
公开(公告)号：US06772300B1
公开(公告)日：2004-08-03
申请号：US09651437
申请日：2000-08-30
申请人： Daniel A. Manseau
发明人： Daniel A. Manseau
IPC分类号： G06F1200
CPC分类号： G06F13/1626
摘要： According to one embodiment, a computer system is disclosed. The computer system comprises a main memory; and a chip set coupled to the main memory. The chip set comprises a transaction memory, a first bank controller and a second bank controller coupled to the transaction memory. The first bank controller stores transaction data to be transmitted to a first bank of main memory within the transaction memory according to a first linked list. The second bank controller stores transaction data to be transmitted to a second bank of main memory within the transaction memory according to a second linked list.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括主存储器; 以及耦合到主存储器的芯片组。芯片组包括事务存储器，第一存储体控制器和耦合到交易存储器的第二存储体控制器。第一银行控制器根据第一链表将交易数据存储在交易存储器内的要发送到主存储器的第一组。第二存储体控制器根据第二链表将事务数据存储到事务存储器内的主存储器的第二存储体。

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