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1. 发明授权

US09368490B2 Enhancement-depletion mode inverter with two transistor architectures 有权
标题翻译：具有两个晶体管架构的增强耗尽型逆变器
公开(公告)号：US09368490B2
公开(公告)日：2016-06-14
申请号：US14526634
申请日：2014-10-29
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L27/088 , H01L29/786
CPC分类号： H01L27/0883 , H01L27/1225 , H01L27/1251 , H01L29/7869
摘要： An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate.
摘要翻译：增强耗尽型逆变器包括负载晶体管和驱动晶体管。负载晶体管具有顶栅结构，其具有第一源极，第一漏极，负载沟道区域，第一半导体层和第一栅极电极。负载栅极电介质位于负载沟道区域中，并具有负载介质厚度。负载晶体管被配置为在耗尽模式下工作。驱动晶体管具有底栅结构，其具有第二源极，第二漏极，驱动沟道区，第二半导体层和第二栅电极。驱动栅极电介质位于驱动沟道区域中，并且具有不同于负载介质厚度的驱动电介质厚度。驱动晶体管被配置为在正常模式或增强模式下操作。第一源电连接到第二漏极和第一栅极。

2. 发明授权

US09299853B1 Bottom gate TFT with multilayer passivation 有权
标题翻译：底栅TFT多层钝化
公开(公告)号：US09299853B1
公开(公告)日：2016-03-29
申请号：US14487161
申请日：2014-09-16
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/12 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/7869
摘要： A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap.
摘要翻译：晶体管包括与衬底接触的栅极。栅极绝缘层至少与栅极接触。无机半导体层与栅极绝缘层接触。存在与无机半导体层的第一部分接触的源电极和与无机半导体层的第二部分接触的漏电极，并且源电极和漏电极被间隙分开。存在与间隙中的至少无机半导体层接触的多层绝缘结构。多层结构包括具有限定第一区域的第一图案的无机介电层; 以及具有限定第二区域的第二图案的聚合物结构。第二区域位于第一区域内，聚合物结构与间隙中的半导体层接触。

3. 发明申请

US20150257260A1 VERTICALLY SPACED ELECTRODE STRUCTURE 有权
标题翻译：垂直间距电极结构
公开(公告)号：US20150257260A1
公开(公告)日：2015-09-10
申请号：US14198658
申请日：2014-03-06
申请人： Carolyn Rae Ellinger
发明人： Carolyn Rae Ellinger
IPC分类号： H05K1/02 , H05K1/09
CPC分类号： H05K1/0284 , C23C16/345 , C23C16/403 , C23C16/405 , C23C16/407 , H01L29/41733 , H01L29/42384 , H01L29/78603 , H01L29/78642 , H01L29/78696 , H01L2924/0002 , H05K1/09 , H05K2201/0137 , H05K2201/0326 , H05K2201/09045 , H01L2924/00
摘要： A vertically separated electrode structure includes a polymeric material post on a substrate. An inorganic material cap covers the top of the post and extends beyond an edge of the post in at least a width dimension to define a first reentrant profile. A first electrode is located over the cap. A second electrode is located over the substrate and not over the post. The second electrode is adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. The first electrode and second electrode have the same material composition and layer thickness.
摘要翻译：垂直分离的电极结构包括在基底上的聚合物材料柱。无机材料盖覆盖柱的顶部并且在至少一个宽度尺寸上延伸超出柱的边缘以限定第一凹槽轮廓。第一电极位于盖上。第二电极位于衬底上并且不在柱上。第二电极在折返轮廓中与柱的边缘相邻，使得当与衬底表面正交测量时，第一电极和第二电极之间的距离大于零。第一电极和第二电极具有相同的材料组成和层厚度。

4. 发明申请

US20150255624A1 VTFT INCLUDING OVERLAPPING ELECTRODES 有权
标题翻译： VTFT包括重叠电极
公开(公告)号：US20150255624A1
公开(公告)日：2015-09-10
申请号：US14198643
申请日：2014-03-06
申请人： Shelby Forrester Nelson , Carolyn Rae Ellinger , Lee William Tutt
发明人： Shelby Forrester Nelson , Carolyn Rae Ellinger , Lee William Tutt
IPC分类号： H01L29/786 , H01L29/10 , H01L29/423
CPC分类号： H01L29/78642 , H01L29/1037 , H01L29/42384 , H01L29/7869
摘要： A vertical transistor includes a substrate and an electrically conductive gate structure having a top surface and including a reentrant profile. A conformal electrically insulating layer that maintains the reentrant profile is in contact with the electrically conductive gate structure and at least a portion of the substrate. A conformal semiconductor layer that maintains the reentrant profile is in contact with the conformal electrically insulating layer. An electrode that extends into the reentrant profile is in contact with a first portion of the semiconductor layer. Another electrode is vertically spaced apart from the electrode, overlaps a portion of the electrode that extends into the reentrant profile, is in contact with a second portion of the semiconductor material layer over the top surface of the electrically conductive gate structure, and is within the reentrant profile.
摘要翻译：垂直晶体管包括基板和具有顶表面并且包括折入轮廓的导电栅极结构。维持凹凸轮廓的保形电绝缘层与导电栅极结构和衬底的至少一部分接触。保持凹凸轮廓的保形半导体层与保形电绝缘层接触。延伸到凹陷轮廓中的电极与半导体层的第一部分接触。另一个电极与电极垂直间隔开，与延伸到凹陷轮廓中的电极的一部分重叠，与导电栅极结构的顶表面上的半导体材料层的第二部分接触，并且位于可重入的资料

5. 发明授权

US09117914B1 VTFT with polymer core 有权
标题翻译： VTFT与聚合物芯
公开(公告)号：US09117914B1
公开(公告)日：2015-08-25
申请号：US14198628
申请日：2014-03-06
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/78642 , H01L29/78603 , H01L29/7869
摘要： A transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the post, extends beyond an edge of the post to define a reentrant profile. A conformal conductive material gate layer is over the edge of the post in the reentrant profile. A conformal insulating material layer is on the gate layer in the reentrant profile. A conformal semiconductor material layer is on the insulating material layer in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap. A second electrode is in contact with a second portion of the semiconductor layer over the substrate and not over the post, and adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface.
摘要翻译：晶体管包括在基板上的聚合材料柱。覆盖柱的无机材料帽延伸超过柱的边缘以限定折返轮廓。保形导电材料栅极层位于折返轮廓中的柱的边缘上。在凹凸轮廓中的栅极层上保形绝缘材料层。保形半导体材料层位于折入型材中的绝缘材料层上。第一电极与帽上的半导体层的第一部分接触。第二电极与衬底上的半导体层的第二部分接触，而不是在柱上，并且邻近在折返轮廓中的柱的边缘，使得第一电极和第二电极之间的距离大于零当与基底表面正交测量时。

6. 发明授权

US09391210B2 Top gate TFT with polymer interface control layer 有权
标题翻译：顶栅TFT与聚合物界面控制层
公开(公告)号：US09391210B2
公开(公告)日：2016-07-12
申请号：US14487184
申请日：2014-09-16
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/10 , H01L29/786 , H01L29/417
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/78606 , H01L29/78642
摘要： A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap.
摘要翻译：晶体管包括衬底和与衬底接触的聚合物层。聚合物层具有限定第一区域的第一图案。聚合物层之上和与其接触的无机半导体层具有限定第二区域的第二图案。第一个区域位于第二个区域内。存在与半导体层的第一部分接触的源电极和与半导体层的第二部分接触的漏电极，并且源电极和漏电极被间隙分开。栅极绝缘层与间隙中的无机半导体层接触。与间隙上的栅极绝缘层接触的栅极。

7. 发明申请

US20160126241A1 ENHANCEMENT-DEPLETION MODE INVERTER WITH TWO TRANSISTOR ARCHITECTURES 有权
标题翻译：具有两个晶体管结构的增强型绝缘模式逆变器
公开(公告)号：US20160126241A1
公开(公告)日：2016-05-05
申请号：US14526634
申请日：2014-10-29
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L27/088 , H01L29/786
CPC分类号： H01L27/0883 , H01L27/1225 , H01L27/1251 , H01L29/7869
摘要： An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate.
摘要翻译：增强耗尽型逆变器包括负载晶体管和驱动晶体管。负载晶体管具有顶栅结构，其具有第一源极，第一漏极，负载沟道区域，第一半导体层和第一栅极电极。负载栅极电介质位于负载沟道区域中，并具有负载介质厚度。负载晶体管被配置为在耗尽模式下工作。驱动晶体管具有底栅结构，其具有第二源极，第二漏极，驱动沟道区，第二半导体层和第二栅电极。驱动栅极电介质位于驱动沟道区域中，并且具有不同于负载介质厚度的驱动电介质厚度。驱动晶体管被配置为在正常模式或增强模式下操作。第一源电连接到第二漏极和第一栅极。

8. 发明申请

US20160079440A1 BOTTOM GATE TFT WITH MULTILAYER PASSIVATION 有权
标题翻译：底层门TFT多层钝化
公开(公告)号：US20160079440A1
公开(公告)日：2016-03-17
申请号：US14487161
申请日：2014-09-16
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/7869
摘要： A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap.
摘要翻译：晶体管包括与衬底接触的栅极。栅极绝缘层至少与栅极接触。无机半导体层与栅极绝缘层接触。存在与无机半导体层的第一部分接触的源电极和与无机半导体层的第二部分接触的漏电极，并且源电极和漏电极被间隙分开。存在与间隙中的至少无机半导体层接触的多层绝缘结构。多层结构包括具有限定第一区域的第一图案的无机介电层; 以及具有限定第二区域的第二图案的聚合物结构。第二区域位于第一区域内，聚合物结构与间隙中的半导体层接触。

9. 发明申请

US20160079429A1 TOP GATE TFT WITH POLYMER INTERFACE CONTROL LAYER 有权
标题翻译：顶盖TFT与聚合物界面控制层
公开(公告)号：US20160079429A1
公开(公告)日：2016-03-17
申请号：US14487184
申请日：2014-09-16
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/786 , H01L29/417
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/78606 , H01L29/78642
摘要： A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap.
摘要翻译：晶体管包括衬底和与衬底接触的聚合物层。聚合物层具有限定第一区域的第一图案。聚合物层之上和与其接触的无机半导体层具有限定第二区域的第二图案。第一个区域位于第二个区域内。存在与半导体层的第一部分接触的源电极和与半导体层的第二部分接触的漏电极，并且源电极和漏电极被间隙分开。栅极绝缘层与间隙中的无机半导体层接触。与间隙上的栅极绝缘层接触的栅极。

10. 发明授权

US09236486B2 Offset independently operable VTFT electrodes 有权
标题翻译：偏移可独立操作的VTFT电极
公开(公告)号：US09236486B2
公开(公告)日：2016-01-12
申请号：US14198647
申请日：2014-03-06
申请人： Shelby Forrester Nelson , Carolyn Rae Ellinger
发明人： Shelby Forrester Nelson , Carolyn Rae Ellinger
IPC分类号： H01L29/80 , H01L29/76 , H01L29/94 , H01L29/66 , H01L29/786 , H01L27/12
CPC分类号： H01L29/78642 , H01L27/1218 , H01L27/1222 , H01L27/1262 , H01L29/42384 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L29/78696
摘要： A multiple vertical transistor device includes a polymeric material post on a substrate. An inorganic material cap extends beyond first and second edge of the post to define first and second reentrant profiles. First and second portions of a conformal conductive gate layer define first and second gates in the first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the first and second reentrant profiles and is in contact with the first and second gates. First and second portions of a semiconductor layer, maintaining the first and second reentrant profiles, are in contact with the conformal electrically insulating layer that is in contact with the first and second gates, respectively. The first and second portions of the semiconductor layer are electrically independent from each other. First and second electrodes are associated with the first gate. Third and fourth electrodes are associated with the second gate.
摘要翻译：多垂直晶体管器件包括在衬底上的聚合物材料柱。无机材料帽延伸超过柱的第一和第二边缘以限定第一和第二折痕轮廓。共形导电栅极层的第一部分和第二部分分别在第一和第二折入轮廓中限定第一和第二栅极。保形电绝缘层保持第一和第二凹槽轮廓并与第一和第二闸门接触。保持第一和第二折入轮廓的半导体层的第一和第二部分分别与与第一和第二栅极接触的保形电绝缘层接触。半导体层的第一和第二部分彼此电独立。第一和第二电极与第一栅极相关联。第三和第四电极与第二栅极相关联。

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