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1. 发明授权

US09287880B2 Integrated circuit device having an injection-locked oscillator 有权
标题翻译：具有注入锁定振荡器的集成电路装置
公开(公告)号：US09287880B2
公开(公告)日：2016-03-15
申请号：US13988615
申请日：2011-11-10
申请人： Marko Aleksic , Brian S. Leibowitz
发明人： Marko Aleksic , Brian S. Leibowitz
IPC分类号： H03L7/24 , H03L1/00 , H03K3/03 , H03L7/083
CPC分类号： H03L1/00 , H03K3/0315 , H03L7/083 , H03L7/24
摘要： A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
摘要翻译：描述了可变注射强度注射锁定振荡器（ILO）。可变注入强度ILO可以基于输入时钟信号输出输出时钟信号。响应于接收功率模式信息，可变注入强度ILO可以相对于输入时钟信号同步地暂停，重新启动，减慢或加速输出时钟信号。具体地说，当输入时钟信号被暂停，重新启动，减速或加速时，可变注入强度ILO可以在相对强的注入下操作。

2. 发明授权

US09094238B2 High-speed signaling systems with adaptable pre-emphasis and equalization 有权
公开(公告)号：US09094238B2
公开(公告)日：2015-07-28
申请号：US13216047
申请日：2011-08-23
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L27/01 , H04L1/00 , H04L7/033 , H04L25/03 , H04L25/497 , H04W52/20 , H04L7/00 , H04L25/02 , H04W52/22
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

3. 发明授权

US08989249B2 High-speed signaling systems with adaptable pre-emphasis and equalization 有权
标题翻译：具有适应性预加重和均衡的高速信号系统
公开(公告)号：US08989249B2
公开(公告)日：2015-03-24
申请号：US13215951
申请日：2011-08-23
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L27/01 , H04L1/00 , H04L7/033 , H04L25/03 , H04L25/497 , H04W52/20 , H04L7/00 , H04L25/02 , H04W52/22
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
摘要翻译：一个信令系统包括一个预先强调的发射机和一个通过高速信号路径相互耦合的均衡接收机。接收机测量从发射机传送的数据的质量。控制器使用该信息和其他信息来自适应地建立适当的发送预加重和接收均衡设置，例如，选择信令系统提供一些最小通信带宽而不超过所需误码率的最低功率设置。

4. 发明授权

US08477835B2 Methods and circuits for asymmetric distribution of channel equalization between devices 有权
公开(公告)号：US08477835B2
公开(公告)日：2013-07-02
申请号：US13103564
申请日：2011-05-09
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H03H7/30
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

5. 发明申请

US20130148709A1 Interface with Variable Data Rate 有权
公开(公告)号：US20130148709A1
公开(公告)日：2013-06-13
申请号：US13633076
申请日：2012-10-01
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC分类号： H04L25/02
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

6. 发明申请

US20130033946A1 FREQUENCY-AGILE STROBE WINDOW GENERATION 有权
标题翻译：频率梯形窗口生成
公开(公告)号：US20130033946A1
公开(公告)日：2013-02-07
申请号：US13545255
申请日：2012-07-10
申请人： Frederick A. Ware , Brian S. Leibowitz , Ely Tsern
发明人： Frederick A. Ware , Brian S. Leibowitz , Ely Tsern
IPC分类号： G11C8/18
CPC分类号： G11C29/023 , G06F13/1689 , G11C7/1066 , G11C29/022 , G11C29/028 , H03K5/135
摘要： The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.
摘要翻译：所公开的实施例涉及在读取访问期间支持频率敏捷选通使能窗口生成的存储器系统的组件。在具体实施例中，该存储器系统包括存储器控制器，其包括定时电路，以使定时使能信号与从读取路径返回的定时信号同步，其中定时信号包括来自读取路径的延迟。在一些实施例中，定时电路还包括两个校准回路。第一校准环路相对于延迟中的与周期相关的延迟跟踪定时使能信号，其中周期相关延迟取决于选通信号的频率。第二校准环路相对于延迟中的与周期无关的延迟跟踪定时使能信号，其中，周期无关延迟不依赖于选通信号的频率。在一些实施例中，级联第一校准回路和第二校准回路。

7. 发明申请

US20120254472A1 CHIP SELECTION IN A SYMMETRIC INTERCONNECTION TOPOLOGY 审中-公开
标题翻译：芯片选择在对称互连拓扑学中
公开(公告)号：US20120254472A1
公开(公告)日：2012-10-04
申请号：US13514977
申请日：2010-12-07
申请人： Frederick A. Ware , Brian S. Leibowitz
发明人： Frederick A. Ware , Brian S. Leibowitz
IPC分类号： G06F3/00
CPC分类号： G06F13/1684 , G11C5/02
摘要： Techniques for distinguishing between symmetrically-connected integrated circuit devices so that each device may be individually selected are disclosed in reference to various embodiments. In one embodiment, a bi-directional data path provided for ongoing data transfer between a master device and multiple nominally identical slave devices is used to receive a merged set of randomly generated values from the slave devices, and then used to return one or more device-select values that enable assignment of a unique chip-identifier (ID) within each slave device. After chip-IDs have been assigned to the slave devices, the master device may issue one or more chip-select signals corresponding to the unique chip ID assigned to a given slave and thereby enable that slave device, exclusively of the others, to participate in a data transfer operation over the bi-directional data path.
摘要翻译：用于区分对称连接的集成电路器件以便可以单独选择每个器件的技术参考各种实施例来公开。在一个实施例中，提供用于主设备和多个名义上相同的从设备之间的正在进行的数据传输的双向数据路径用于从从设备接收随机生成的值的合并集合，然后用于返回一个或多个设备 - 选择允许在每个从设备中分配唯一的芯片标识符（ID）的值。在将芯片ID分配给从设备之后，主设备可以发出与分配给给定从设备的唯一芯片ID相对应的一个或多个芯片选择信号，从而使得其他专用设备能够参与在双向数据路径上的数据传输操作。

8. 发明申请

US20100272215A1 Signaling with Superimposed Differential-Mode and Common-Mode Signals 有权
标题翻译：信号与叠加的差分模式和共模信号
公开(公告)号：US20100272215A1
公开(公告)日：2010-10-28
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jacha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jacha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H04L27/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,—the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

9. 发明申请

US20140210545A1 ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATION 有权
标题翻译：具有可变负载补偿的片上稳压器
公开(公告)号：US20140210545A1
公开(公告)日：2014-07-31
申请号：US14241843
申请日：2012-08-31
申请人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
发明人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC分类号： G05F1/46
CPC分类号： G05F1/462 , G11C5/147
摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
摘要翻译：集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。该电路根据数据从电压调节器抽取可变量的功率。电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

10. 发明授权

US08743973B2 Receiver resistor network for common-mode signaling 失效
标题翻译：用于共模信号的接收电阻网络
公开(公告)号：US08743973B2
公开(公告)日：2014-06-03
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入以及输出，以提供从在输入节点处接收的信号的共模分量得到的信号。

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