专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5761443A Computer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral bus 失效
标题翻译：计算机系统采用总线转换桥接器，用于将驻留在多路复用外设总线上的主设备连接到驻留在分割地址，分割数据复用外围总线
公开(公告)号：US5761443A
公开(公告)日：1998-06-02
申请号：US487063
申请日：1995-06-07
申请人： Uwe Kranich
发明人： Uwe Kranich
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A multiple-transaction peripheral bus is provided with multiplexed address and data lines which is particularly adapted for portable applications. The multiple-transaction peripheral bus accommodates compatibility with existing hardware designs for a higher performance bus system with minimal conversion logic. A bus conversion bridge provides an interface between a 32-bit Peripheral Component Interconnect (PCI) bus and a 16-bit transaction Address/Data (A/D) which is associated with half the number of multiplexed address/data lines in comparison with the 32-bit PCI bus. The PCI bus accommodates data transfers between master and slave devices associated therewith, as does the narrower multiple-transaction A/D bus. The bus conversion bridge accommodates data transfers between the two buses, allowing a master device on one bus to communicate with a slave device on the other bus. The bus conversion bridge accomplishes this by 1) splitting both the 32-bit address/4-bit bus command and 32-bit data/4-bit byte enables received from the PCI bus during respective address and data phases into separate 16-bit/2-bit packets, and transmitting these packets over the multiple-transaction A/D bus during separate bus cycles, and 2) assembling multiple 16-bit address/2-bit bus command and multiple 16-bit data/2-bit byte enables received from the multiple-transaction A/D bus during separate bus cycles into single 32-bit/4-bit packets, and transmitting these packets over the PCI bus during respective address and data phases. Thus the bus conversion bridge allows a portable computer system with a narrower, 16-bit multiple-transaction A/D bus to communicate with peripherals on a wider, 32-bit PCI bus.
摘要翻译：多事务外设总线提供多路地址和数据线，特别适用于便携式应用。多事务外设总线适应与现有硬件设计的兼容性，用于具有最小转换逻辑的更高性能总线系统。总线转换桥提供32位外设组件互连（PCI）总线与16位事务地址/数据（A / D）之间的接口，该地址/数据（A / D）与多路复用的地址/数据线的数量相比较，与 32位PCI总线。 PCI总线适应与其相关的主设备和从设备之间的数据传输，更窄的多事务A / D总线也是如此。总线转换桥适应两条总线之间的数据传输，允许一条总线上的主设备与另一条总线上的从设备进行通信。总线转换桥通过以下方式实现：1）在相应的地址和数据阶段，将32位地址/ 4位总线命令和32位数据/ 4位字节分别从PCI总线接收到单独的16位/ 2位数据包，并在单独的总线周期内通过多事务A / D总线传输这些数据包，以及2）组合多个16位地址/ 2位总线命令和多个16位数据/ 2位字节在单独的总线周期内从多事务A / D总线接收到单个32位/ 4位数据包，并在相应的地址和数据阶段通过PCI总线传输这些数据包。因此，总线转换桥允许具有较窄的16位多事务A / D总线的便携式计算机系统与较宽的32位PCI总线上的外设进行通信。

2. 发明授权

US5768584A ROM chip enable encoding method and computer system employing the same 失效
标题翻译： ROM芯片使能编码方法和采用该方法的计算机系统
公开(公告)号：US5768584A
公开(公告)日：1998-06-16
申请号：US710047
申请日：1996-09-10
申请人： James R. MacDonald , Douglas D. Gephardt
发明人： James R. MacDonald , Douglas D. Gephardt
IPC分类号： G11C17/00 , G06F9/445 , G06F12/00 , G06F12/06
CPC分类号： G06F9/4401 , G06F12/0653
摘要： A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines. In this configuration, each output line of the decoder is coupled to a respective bank enable input line of the ROM banks. In either configuration, the chip enable lines are driven in a mutually exclusive relationship during system boot to access the boot code (stored within one of the ROM banks). Subsequently, the encoding of the chip enable signals at the chip enable output lines of the memory controller is dependent upon configuration information stored in a configuration register.
摘要翻译：非易失性存储器芯片使能编码方法允许在公共存储器阵列中存储引导代码和用户应用软件。芯片使能编码方法还允许在非易失性存储器阵列内提供可变数量的存储体，并且在固件选择阵列配置之前允许系统上电并执行引导代码。在一个实施例中，存储器控制器包括用于选择性地启用多个ROM组的四个芯片使能输出线。其中一个ROM库包括在系统引导期间由系统微处理器执行的引导代码。如果用户需要由四个ROM组组成的ROM阵列，则每个ROM组连接有单独的芯片使能输出线。如果用户需要由例如八个ROM组组成的ROM阵列，则外部解码器可以连接到四个芯片使能输出线。在该配置中，解码器的每个输出线耦合到ROM组的相应的bank使能输入线。在任一配置中，芯片使能线在系统引导期间以相互排斥的关系被驱动以访问引导代码（存储在ROM库之一内）。随后，存储器控制器的芯片使能输出线处的芯片使能信号的编码取决于存储在配置寄存器中的配置信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式