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    • 6. 发明授权
    • 통신 시스템에서 신호 수신 장치 및 방법
    • 用于在通信系统中接收信号的设备和方法
    • KR100800853B1
    • 2008-02-04
    • KR1020050049406
    • 2005-06-09
    • 삼성전자주식회사
    • 조현상박윤상송봉기
    • H04L27/22
    • H03M13/25H03M13/256H04L1/0052H04L1/0059H04L1/0066
    • 본 발명은 통신 시스템의 신호 수신 장치에서, 다수의 디매핑 방식중 특정 디매핑 방식에 상응하게 입력 신호를 디매핑하여 특정 로그 우도비(LLR: Log-Likelihood Rate)값을 생성하고, 상기 특정 LLR 값을 상기 다수의 LLR 서브 버퍼들중 특정 LLR 서브 버퍼에 버퍼링하도록 제어하고, 상기 LLR 버퍼에 버퍼링되어 있는 LLR 값을 읽도록 제어하며, 상기 특정 LLR 서브 버퍼는 상기 특정 디매핑 방식에 상응하게 생성되는 LLR 값을 버퍼링하는 LLR 서브 버퍼임을 특징으로 한다.
      LLR 버퍼, 변조 방식, 디매핑 방식, LLR 값, LLR 서브 버퍼
    • 在本发明中用于通信系统的信号接收装置中,通过映射D.多个特定数似然比中解映射对应于所述输入信号指定的方法解映射方案的(LLR:对数似然率)生成的值,和预定的LLR 其中,所述多个控制为被缓冲到一个特定的LLR子缓冲器,LLR子缓冲器的值控制来读取在LLR缓冲器中缓冲的LLR值,并且对应地产生的特定解映射方案中的特定LLR子缓冲器 还有一个用于缓存LLR值的LLR子缓冲区。
    • 7. 发明公开
    • 통신 시스템에서 신호 수신 장치 및 방법
    • MODEM LLR BUFFER DEVICE
    • KR1020060128180A
    • 2006-12-14
    • KR1020050049406
    • 2005-06-09
    • 삼성전자주식회사
    • 조현상박윤상송봉기
    • H04L27/22
    • H03M13/25H03M13/256H04L1/0052H04L1/0059H04L1/0066
    • An apparatus and a method for receiving a signal in a communication system are provided to enhance efficiency by minimizing a delay due to a buffering operation and reducing a size of a memory. An LLR(Log-Likelihood Rate) demapper(110) outputs an LLR value according to an input data mode. A buffer memory(150) includes two or more sub-buffers for storing the LLR value. A write control unit(120) receives the LLR value from the LLR demapper and generates a write address for storing the LLR value in the buffer memory. A read address generation unit(130) generates a read address for reading the LLR value stored in the buffer memory.
    • 提供一种用于在通信系统中接收信号的装置和方法,以通过最小化由于缓冲操作引起的延迟并减小存储器的大小来提高效率。 LLR(对数似然率)解映射器(110)根据输入数据模式输出LLR值。 缓冲存储器(150)包括用于存储LLR值的两个或多个子缓冲器。 写控制单元(120)从LLR解映射器接收LLR值,并产生用于在缓冲存储器中存储LLR值的写地址。 读取地址生成单元(130)生成用于读取存储在缓冲存储器中的LLR值的读取地址。
    • 8. 发明授权
    • 콘볼루션디코더의트렐리스디매퍼
    • KR100455489B1
    • 2005-01-13
    • KR1019960039601
    • 1996-09-13
    • 톰슨 콘슈머 일렉트로닉스, 인코포레이티드
    • 쿠마르라마스와미존시드니스튜워트
    • H03M13/25
    • H03M13/256H03M13/25
    • The trellis demapper, which is capable of demapping 8-PSK and 16, 32, 64, 128 and 256 QAM trellis codes, comprises respective I-channel, Q-channel and remapper RAMs, an 8-PSK demapper logic means and a MUX selects. Each of the RAMs includes a lookup table is selectively programmed for each of the QAM codes. The I-channel RAM (400) and the Q-channel RAM (402), each of which has a storage capacity of 768 bits, directly forwards their respective outputs through the MUX (408) selects as the trellis demapper (406) output in response to a QAM trellis code which is an even power of 2 (i.e., 16, 64 or 256) being selected. In response to a QAM trellis code which is an odd power of 2 (i.e., 32 or 128) being selected, the respective outputs of the I-channel RAM and the Q-channel RAM are applied as inputs to the remapper RAM (404), which has a storage capacity of 320 bits, and the output of the remapper RAM is forwarded through the MUX selects as the trellis demapper output. In response to an 8-PSK trellis code being selected, the output of the 8-PSK demapper logic means is forwarded through the MUX selects as the trellis demapper output. This configuration is structurally efficient and requires minimum storage requirements compared to a trellis code demapper employing ROM storage for the 16, 32, 64, 128 and 256 QAM and 8-PSK trellis codes.
    • 能够对8-PSK和16,32,64,128和256QAM格码进行解映射的格构去映射器包括各自的I通道,Q通道和再映射器RAM,8-PSK去映射器逻辑装置和MUX选择器 。 每个RAM包括为每个QAM代码有选择地编程的查找表。 每个存储容量为768位的I通道RAM(400)和Q通道RAM(402)通过MUX(408)直接转发它们各自的输出作为网格解映射器(406)输出 响应于选择2(即,16,64或256)的偶数幂的QAM格码。 响应于选择2(即32或128)的奇数次幂的QAM格码,I通道RAM和Q通道RAM的相应输出作为输入施加到再映射器RAM(404) ,其具有320位的存储容量,并且通过MUX选择将再映射RAM的输出作为网格解映射器输出来转发。 响应于选择8-PSK网格代码,8-PSK去映射器逻辑装置的输出通过MUX选择被转发为网格去映射器输出。 与使用ROM存储器的16,32,64,128和256 QAM和8-PSK网格代码的网格代码去映射器相比,此配置在结构上是高效的并且需要最小的存储需求。 <图像>
    • 9. 发明公开
    • 오정정 보호 방법, 저장 장치, 데이터 세트 보호 방법,데이터 저장 장치, 및 에러 정정 코드
    • 错误保护方法,存储设备,数据设置保护方法,数据存储设备和错误校正码,特别关于用于数据存储的集成区段格式(ISF)和错误校正码(ECC)编码和解码过程 设备或通信设备和系统
    • KR1020040044103A
    • 2004-05-27
    • KR1020030076685
    • 2003-10-31
    • 인터내셔널 비지네스 머신즈 코포레이션
    • 아사노,히데오하스너,마틴오렐리아노헤이스,닐스노버트헤즐러,스티븐알.타무라,테츄야
    • G11B20/18
    • H03M13/25G06F11/1076G06F2211/104H03M13/1515H03M13/29H03M13/47
    • PURPOSE: A miscorrection protecting method, a storage device, a data set protecting method, a data storage device, and an ECC are provided to protect a miscorrection caused by a parity sector modification in an on-drive-raid system, thereby protecting a miscorrection caused by a parity sector updating in an ISF(Integrated Sector Format)-ECC system within an on-drive-parity sector system. CONSTITUTION: When a sequence of digital binary data is recorded on a disk(1), the digital binary data are temporarily located within a buffer(15), and are converted according to recording paths or channels(17,19,7,5,3) having plural stages. Binary data elements proceed through the ECC recording processor(17) by moving from the buffer(15). In the processor(17), data bytes are mapped into codewords extracted from linear blocks or cyclic codes. Each codeword is mapped into other bands or spectrum shaping codes or run length limited within the signal shaping unit(19), and is changed into time-varying signals. The time-varying signals are provided through the interface(7), and are supplied to the other converter(3).
    • 目的:提供一种错误修复保护方法,存储设备,数据集保护方法,数据存储设备和ECC,以保护由驱动器系统中的奇偶校验扇区修改引起的错误修复,从而保护错误修复 由在驱动器间奇偶校验扇区系统中的ISF(集成扇区格式)-ECC系统中的奇偶校验扇区更新引起的。 构成:当数字二进制数据序列记录在磁盘(1)上时,数字二进制数据暂时位于缓冲器(15)内,并根据记录路径或通道(17,19,7,5, 3)具有多个阶段。 二进制数据元素通过从缓冲器(15)移动通过ECC记录处理器(17)进行。 在处理器(17)中,将数据字节映射到从线性块或循环码提取的码字。 每个码字被映射到在信号整形单元(19)内限制的其他频带或频谱整形码或游程长度,并被改变为时变信号。 时变信号通过接口(7)提供,并被提供给另一转换器(3)。