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    • 3. 发明公开
    • 출력 버퍼회로
    • 输出缓冲电路
    • KR1020070007439A
    • 2007-01-16
    • KR1020050062053
    • 2005-07-11
    • 삼성전기주식회사
    • 이연중최원태박찬우김병훈
    • H03K19/0175H03K19/0185
    • H03F3/347H03F1/301H03F1/303H03F3/45753H03F2203/45212
    • An output buffer circuit is provided to perform a high speed data transfer, miniaturize an output buffer circuit, and reduce a material cost by using a small number of switching elements and resistances. In an output buffer circuit, a plurality of input stages(201a-201f) supplies an input voltage to one terminal and a magnetic output voltage to the other terminal. A class AB output stage(204a,204b) increases current in an output stage when a difference between the input voltage and the output voltage becomes above 0. A floating current source(202a-202d) biases the class AB output stage(204a,204b). A summing circuit(203a-203h) sums a current provided from the input stage and an inner current provided from the floating current source(202a-202d). And, an offset compensation circuit compensates the offset voltage by sensing the offset voltage.
    • 提供输出缓冲电路以执行高速数据传输,使输出缓冲电路小型化,并且通过使用少量的开关元件和电阻来降低材料成本。 在输出缓冲电路中,多个输入级(201a-201f)向一个端子提供输入电压,并向另一端提供磁输出电压。 AB类输出级(204a,204b)在输入电压和输出电压之间的差变为0以上时,在输出级增加电流。浮动电流源(202a〜202d)偏置AB类输出级(204a,204b) )。 求和电路(203a-203h)将从输入级提供的电流与从浮动电流源(202a-202d)提供的内部电流相加。 并且,偏移补偿电路通过感测偏移电压来补偿偏移电压。
    • 5. 发明公开
    • 반도체 집적회로의 감지 증폭장치
    • 用于半导体集成电路的感应放大器件
    • KR1020010009504A
    • 2001-02-05
    • KR1019990027890
    • 1999-07-10
    • 삼성전자주식회사
    • 심재윤장현순정우섭김경호
    • G11C7/06
    • H03F3/347G11C7/062G11C7/065H03F3/45183H03F3/4565H03F3/72H03F2203/45418H03F2203/45562H03F2203/45571H03F2203/45574H03F2203/45644H03F2203/45652H03F2203/45674H03K5/2481
    • PURPOSE: A sense amplification device for a semiconductor memory device is provided to stabilize an operation of a latch circuit connected with an output terminal of the sense amplification device by reducing an average voltage level of an output signal of the sense amplification device though a supply voltage increases, and to easily adjust a voltage gain. CONSTITUTION: The device includes a sense amplifier(40) amplifying an input signal and an inverting input signal, a complete differential amplifier(42) amplifying an output of the sense amplifier, and a latch(44) latching an output of the complete differential amplifier. The complete differential amplifier includes the first and second differential amplifiers and an output voltage level control circuit. The first differential amplifier(MP9,MP10,MN12,MN13) increases the output of the complete differential amplifier when the input signal is higher than the inverting input signal and decreases the output when vice versa. The second differential amplifier(MP11,MP12,MN14,MN15) decreases the inverting output of the complete differential amplifier when the input signal is higher than the inverting input signal and decreases the output when vice versa. The output voltage level control circuit(60) controls the output signal and the inverting output signal.
    • 目的:提供一种用于半导体存储器件的感测放大装置,用于通过降低感测放大装置的输出信号的平均电压电平来稳定通过感测放大装置的输出端连接的锁存电路的操作, 增加,并易于调整电压增益。 构成:该器件包括放大输入信号和反相输入信号的读出放大器(40),放大读出放大器的输出的完整差分放大器(42)和锁存整个差分放大器的输出的锁存器(44) 。 完整的差分放大器包括第一和第二差分放大器以及输出电压电平控制电路。 当输入信号高于反相输入信号时,第一个差分放大器(MP9,MP10,MN12,MN13)增加了整个差分放大器的输出,反之亦然。 当输入信号高于反相输入信号时,第二个差分放大器(MP11,MP12,MN14,MN15)会降低整个差分放大器的反相输出,反之亦然。 输出电压电平控制电路(60)控制输出信号和反相输出信号。