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1. 发明公开

KR20180057063A 전력 반도체 소자 및 그 동작방법 有权
公开(公告)号：KR20180057063A
公开(公告)日：2018-05-30
申请号：KR20160155212
申请日：2016-11-21
申请人： 현대오트론 주식회사
发明人： LEE JU HWAN
IPC分类号： H01L29/739 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/7393 , H01L21/823493 , H01L29/42312 , H01L29/66325
摘要： 본발명은기판상에배치된제 1 게이트전극; 상기기판내에서상기제 1 게이트전극의양단에각각이격배치된한 쌍의제 1 도전형의웰(well) 영역; 상기한 쌍의제 1 도전형의웰 영역사이에위치한제 2 도전형의웰(well) 영역; 상기제 2 도전형의웰 영역및 상기한 쌍의제 1 도전형의웰 영역의하부에위치한제 2 도전형의에피(epi)층영역; 및상기제 1 도전형의웰 영역과이격되어, 상기제 2 도전형의에피층영역및/또는상기제 2 도전형의웰 영역내에배치된제 2 게이트전극;을포함하는, 전력반도체소자를제공한다.

2. 发明公开

KR1020140107345A 실리콘 기판에 집적 가능한 화합물 터널링 전계효과 트랜지스터 및 그 제조방법 有权
标题翻译：集成在硅基板上的复合隧道场效应晶体管及其制造方法
公开(公告)号：KR1020140107345A
公开(公告)日：2014-09-04
申请号：KR1020147018033
申请日：2011-12-30
申请人： 서울대학교산학협력단 , 경북대학교 산학협력단 , 더 보드 오브 트러스티즈 오프 더 리랜드 스탠포드 쥬니어 유니버시티
发明人： 박병국 , 조성재 , 강인만
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/775 , H01L29/0657 , H01L29/267 , H01L29/42312 , H01L29/66356 , H01L29/66439 , H01L29/7391
摘要： The present invention provides a compound tunneling field effect transistor integrated on a silicon substrate, and a method of fabricating the same. The present invention enables to increase tunneling efficiency with an abrupt band slope by forming a source region with a material having a bandgap of at least 0.4 electron volts (eV) narrower than that of silicon, to increase a driving current (ON current) by forming a channel region with a material having almost no difference in lattice constant from a source region having a high electron mobility at least 5 times higher than that of silicon, and to simultaneously increase ON/OFF current ratio to a great amount by forming a drain region with a material having a bandgap wider than or equal to that of a channel region material to restrain OFF current to the utmost. Furthermore, the present invention enables to easily form tunneling field effect transistors having various threshold voltages in accordance to the circuit designs by adding a specific material (e.g. aluminum) have an electron affinity less than that of a source region material in the process of forming a channel region.
摘要翻译：本发明提供集成在硅衬底上的复合隧道场效应晶体管及其制造方法。本发明能够通过形成具有比硅的带隙小至少0.4电子伏特（eV）的带隙的材料的源极区域，通过形成具有突变带斜率的隧道效率来增加驱动电流（导通电流），通过形成具有与具有高电子迁移率的源极区域的晶格常数几乎没有差异的材料的沟道区域比硅的至少5倍，并且通过形成漏极区域同时将导通/截止电流比增加到大量具有宽度大于或等于沟道区域材料的带隙的材料以最大限度地截止关断电流。此外，本发明能够根据电路设计容易地形成具有各种阈值电压的隧道场效应晶体管，所述隧道效应晶体管具有在形成栅极的过程中具有小于源区材料的电子亲和力的特定材料（例如铝）渠道区域。

3. 发明公开

KR1020110125385A 매립게이트를 구비한 반도체 장치 및 그 제조방법 有权
标题翻译：具有开口门的半导体器件及其制造方法
公开(公告)号：KR1020110125385A
公开(公告)日：2011-11-21
申请号：KR1020100044878
申请日：2010-05-13
申请人： 에스케이하이닉스 주식회사
发明人： 김명옥 , 박보민 , 이춘희 , 박상희 , 김태한
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66348 , H01L21/02244 , H01L29/42312 , H01L29/4232
摘要： PURPOSE: A semiconductor device equipped with a buried gate and a manufacturing method thereof are provided to prevent the generation of short by forming the upper side of a barrier metal film to be lower than the upper side of a gate electrode and increasing the interval between a plug and the barrier metal film. CONSTITUTION: A plurality of recess patterns(23) is formed on a substrate. A gate insulating layer(24) is formed on the surface of the recess patterns. A barrier metal film is formed according to the surface of a structure which includes the gate insulating layer. A gate conductive film is formed in order to cover the front surface of the substrate on the barrier metal film. A gate electrode(26B) which is buried to the recess pattern is formed by flattening the gate conductive film.
摘要翻译：目的：提供一种配备有掩埋栅极的半导体器件及其制造方法，以通过将阻挡金属膜的上侧形成为低于栅电极的上侧来防止产生短路，并且增加间隔插头和阻挡金属膜。构成：在基板上形成多个凹部图案（23）。在凹槽图案的表面上形成栅绝缘层（24）。根据包括栅极绝缘层的结构的表面形成阻挡金属膜。形成栅极导电膜以覆盖阻挡金属膜上的衬底的前表面。通过使栅极导电膜变平而形成埋入凹部图形的栅电极（26B）。

4. 发明授权

KR101084019B1 상보성 스핀 트랜지스터 논리회로 失效
标题翻译：补充旋转晶体管逻辑电路
公开(公告)号：KR101084019B1
公开(公告)日：2011-11-16
申请号：KR1020100044330
申请日：2010-05-12
申请人： 한국과학기술연구원
发明人： 구현철 , 한석희 , 장준연 , 김형준 , 최준우
IPC分类号： H01L29/82 , H01L29/772 , H01L29/78 , H01L27/105
CPC分类号： H03K19/091 , B82Y10/00 , G11C11/16 , H03K19/18 , H01L29/42312 , H01L29/78618 , H01L29/78624 , H01L29/78696
摘要： PURPOSE: A complementary spin transfer logic circuit is provided to prevent the oxidation and denaturalization of a channel structure by forming an InAs capping layer on the channel structure. CONSTITUTION: A source(103) is arranged on a semiconductor substrate(101). A spin-polarized electron is injected to a channel structure(200) through the source. The spin-polarized electron is injected to a drain(104) via the channel structure. A gate electrode(106) is arranged on the source, drain, and channel structure. The gate electrode controls the spin of electrons passing through a channel layer included in the channel structure.
摘要翻译：目的：提供互补的自旋转移逻辑电路，以通过在通道结构上形成InAs覆盖层来防止通道结构的氧化和变性。构成：源（103）布置在半导体衬底（101）上。自旋极化电子通过源被注入到通道结构（200）中。自旋极化电子通过沟道结构注入漏极（104）。栅极电极（106）布置在源极，漏极和沟道结构上。栅电极控制通过通道结构中包括的沟道层的电子的自旋。

5. 发明公开

KR1020110119356A 반도체 소자의 트랜지스터 및 그 형성방법 有权
标题翻译：半导体器件的晶体管及其形成方法
公开(公告)号：KR1020110119356A
公开(公告)日：2011-11-02
申请号：KR1020100039014
申请日：2010-04-27
申请人： 에스케이하이닉스 주식회사
发明人： 장경철
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/401 , H01L21/265 , H01L21/823456 , H01L21/823481 , H01L27/10876 , H01L27/10891 , H01L29/4236 , H01L29/4966 , H01L29/42312
摘要： PURPOSE: A transistor of a semiconductor device and a forming method thereof are provided to reduce the read and write time of a semiconductor device by maintaining the threshold voltage of a transistor. CONSTITUTION: A recess(22) is formed on a semiconductor substrate(10) with a preset depth. A first gate electrode(26) is formed in the recess. A second gate electrode(27) is formed on the upper side of the first gate electrode. The second gate electrode has ions with one of nitrogen, oxygen, arsenic, aluminum, and hydrogen. The first and second gate electrodes have TiN, TaN or Mo.
摘要翻译：目的：提供半导体器件的晶体管及其形成方法，以通过维持晶体管的阈值电压来减小半导体器件的读取和写入时间。构成：在具有预设深度的半导体衬底（10）上形成凹部（22）。第一栅电极（26）形成在凹部中。第二栅电极（27）形成在第一栅电极的上侧。第二栅电极具有氮，氧，砷，铝和氢之一的离子。第一和第二栅电极具有TiN，TaN或Mo。

6. 发明公开

KR1020110087538A 반도체 장치 및 그 제조방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020110087538A
公开(公告)日：2011-08-03
申请号：KR1020100007004
申请日：2010-01-26
申请人： 에스케이하이닉스 주식회사
发明人： 고준영
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/041 , H01L21/8238 , H01L29/42312
摘要： PURPOSE: A semiconductor device is provided to prevent threshold voltage shift and DIBL(Drain Induced Barrier Lower) characteristic deterioration by including a first conductive electrode with a complementary and overlapped conductive type with a second impurity area. CONSTITUTION: A gate comprises a second conductive electrode(33) on a substrate with the second conductive type and a first conductive electrode(35) on both sides of a second conductive electrode. The first impurity area(39) of the second conductive type is formed on both side of the substrate of the gate. The second impurity area(40) of the second conductive type is overlapped with the first conductive type electrode by being extended from the first impurity area. The first conductive type and the second conductive type are complementary each other. The second conductive type is n-type if first conductive type is p-type and the second conductive type is p-type if first conductive type is n-type.
摘要翻译：目的：提供一种半导体器件，用于通过包括具有第二杂质区域的具有互补且重叠的导电类型的第一导电电极来防止阈值电压漂移和DIBL（漏极诱导阻挡层较低）特性劣化。构成：栅极包括在具有第二导电类型的衬底上的第二导电电极（33）和在第二导电电极两侧的第一导电电极（35）。第二导电类型的第一杂质区（39）形成在栅极的基板的两侧。第二导电类型的第二杂质区域（40）通过从第一杂质区域延伸而与第一导电型电极重叠。第一导电类型和第二导电类型彼此互补。如果第一导电类型是p型，则第二导电类型是n型，并且如果第一导电类型是n型，则第二导电类型是p型。

7. 发明公开

KR1020110086932A 반도체 장치 및 그 제조방법 无效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020110086932A
公开(公告)日：2011-08-02
申请号：KR1020100006332
申请日：2010-01-25
申请人： 에스케이하이닉스 주식회사
发明人： 이상현
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/42312 , H01L21/02225 , H01L29/41725 , H01L29/4232
摘要： PURPOSE: A semiconductor apparatus and a manufacturing method of the same are provided to prevent an increasing junction leakage current due to an increasing degree of integration, an increasing tunneling leakage current due to increasing electric field, and characteristic deterioration of a semiconductor apparatus due to an increasing leakage current. CONSTITUTION: A semiconductor apparatus includes a gate electrode(35), a gate insulating layer(32A), a drain region(D), and a source region(S). The gate electrode is located on a substrate. The gate insulating layer intervenes between the gate electrode and the substrate, and the thickness at one edge of the gate electrode is locally thicker. The drain region and source region are respectively formed on one side of the gate electrode and another side of the substrate and has an asymmetric structure.
摘要翻译：目的：提供一种半导体装置及其制造方法，以防止由于集成度的增加而导致的结漏电流增加，由于电场增加引起的隧道漏电流增加，以及因半导体装置的特性劣化增加泄漏电流。构成：半导体装置包括栅极电极（35），栅极绝缘层（32A），漏极区域（D）和源极区域（S）。栅电极位于基板上。栅极绝缘层介于栅电极和衬底之间，并且栅电极的一个边缘处的厚度局部变厚。漏极区域和源极区域分别形成在栅电极的一侧和衬底的另一侧上，并且具有不对称结构。

8. 发明公开

KR1020110064893A 반도체 메모리 소자의 채널 영역 형성방법 失效
标题翻译：在半导体存储器件中制作通道区域的方法
公开(公告)号：KR1020110064893A
公开(公告)日：2011-06-15
申请号：KR1020090121664
申请日：2009-12-09
申请人： 에스케이하이닉스 주식회사
发明人： 노재윤
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L21/2253 , H01L21/0465 , H01L29/0626 , H01L29/42312 , H01L29/49 , H01L29/78696
摘要： PURPOSE: A method for forming a channel area of a semiconductor memory device is provided to implant ions for adjusting a threshold voltage with a different condition for each areas using one ion implanting mask, thereby simplifying ion implanting processes for adjusting a threshold voltage. CONSTITUTION: A semiconductor substrate includes first to third areas. An ion implanting mask(105) includes first, second, and third openings(107a,107b,107c). The ion implanting mask is formed on the substrate. Ions for adjusting a threshold voltage are implanted into a third area through the third openings. Ions for adjusting a threshold voltage are implanted into a second area through the second openings. Ions for adjusting a threshold voltage are implanted into a first area through the first openings.
摘要翻译：目的：提供一种用于形成半导体存储器件的通道区域的方法，以使用一个离子注入掩模来为每个区域注入用于调整具有不同条件的阈值电压的离子，从而简化用于调整阈值电压的离子注入过程。构成：半导体衬底包括第一至第三区域。离子注入掩模（105）包括第一，第二和第三开口（107a，107b，107c）。在衬底上形成离子注入掩模。用于调节阈值电压的离子通过第三开口植入第三区域。用于调节阈值电压的离子通过第二开口注入第二区域。用于调节阈值电压的离子通过第一开口注入第一区域。

9. 发明公开

KR1020110059365A 반도체 장치 有权
标题翻译：半导体器件
公开(公告)号：KR1020110059365A
公开(公告)日：2011-06-02
申请号：KR1020090116075
申请日：2009-11-27
申请人： 매그나칩 반도체 유한회사
发明人： 차재한 , 이경호 , 김선구 , 최형석 , 김주호 , 채진영 , 오인택
IPC分类号： H01L29/78
CPC分类号： H01L29/42312 , H01L21/108 , H01L29/7813 , H01L29/78696
摘要： PURPOSE: A high voltage semiconductor device is provided to prevent the deterioration of the operation property of a semiconductor device by forming an overlapped area between a gate electrode and a first impurity area on an inactive area. CONSTITUTION: An active area(34) has a structure with a first conductive type first well and a second conductive type second well. A first conductive type first impurity area is formed on the first well. A gate electrode(41) crosses the first well and the second well on the substrate. An overlapped area is formed by overlapping the first impurity area with the gate electrode of the inactive area and is located in the overlapped area of the first well and the gate electrode in the inactive area.
摘要翻译：目的：提供一种高电压半导体器件，通过在无源区域上形成栅电极和第一杂质区域之间的重叠区域来防止半导体器件的操作性能的劣化。构成：有源区域（34）具有第一导电类型的第一阱和第二导电类型的第二阱的结构。第一导电型第一杂质区形成在第一阱上。栅电极（41）穿过衬底上的第一阱和第二阱。通过使第一杂质区域与非活性区域的栅电极重叠而形成重叠区域，并且位于第一阱和非活性区域中的栅电极的重叠区域中。

10. 发明公开

KR1020110051819A 반도체 소자 및 그의 형성 방법 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：KR1020110051819A
公开(公告)日：2011-05-18
申请号：KR1020090108595
申请日：2009-11-11
申请人： 에스케이하이닉스 주식회사
发明人： 김인구
IPC分类号： H01L21/336 , H01L21/28 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/02068 , H01L21/2253 , H01L21/8249 , H01L27/0251 , H01L29/42312
摘要： PURPOSE: A semiconductor device and a forming method thereof are provided to form a poly silicon layer between a gate electrode and a semiconductor substrate, thereby easily controlling a gate threshold voltage. CONSTITUTION: An active area(104) defined by a device separation film(102) is formed on a semiconductor substrate(100). A gate structure includes a dielectric object and an electrode. The gate structure is formed on the semiconductor substrate. A poly silicon layer(108) is formed on a recess in the device separation film and the active area. A dielectric film is formed on the poly silicon layer. A gate electrode(110) is formed on the dielectric film.
摘要翻译：目的：提供半导体器件及其形成方法以在栅电极和半导体衬底之间形成多晶硅层，从而容易地控制栅极阈值电压。构成：在半导体衬底（100）上形成由器件分离膜（102）限定的有源区（104）。栅极结构包括电介质物体和电极。栅极结构形成在半导体衬底上。在器件分离膜和有源区域的凹部上形成多晶硅层（108）。在多晶硅层上形成电介质膜。在电介质膜上形成栅电极（110）。

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