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    • 1. 发明公开
    • 기밀 보호 상 전이 장치
    • 安全相变设备
    • KR1020070003857A
    • 2007-01-05
    • KR1020067016160
    • 2005-02-08
    • 에너지 컨버젼 디바이시즈, 아이엔씨.
    • 오브신스키스탠포드알.코헨모럴에이치.
    • G11C11/00
    • G11C7/24G11C13/0004G11C13/003G11C13/0059G11C2213/75H01L27/2436H01L45/06H01L45/1233H01L45/144
    • An electronic device for securing the contents of data storage and processing elements. The device includes a security element and a phase-change element connected in a parallel arrangement. The security element is a three-terminal device, such as a conventional transistor or three-terminal phase-change device, having an ON state and an OFF state which differ with respect to resistance and regulate electronic access to the phase-change element by controlling the flow of electrical current applied to the parallel combination. In the ON state, the resistance of the security element is less than that of the phase-change element, thereby preventing, inhibiting or confusion a determination of the resistance of the phase-change element. In this PROTECT mode, the contents of the phase-change element are secured. In the OFF state, the resistance of the security element is greater than that of the phase-change material so that the resistance of the parallel combination approaches that of the phase-change element. In this READ mode, the resistance and information content of the phase-change element can be determined. The phase-change element includes a phase-change material and is preferably a chalcogenide based element. The phase-change element may perform a storage or processing function and includes registers and weighting devices as preferred embodiments. ® KIPO & WIPO 2007
    • 一种用于保护数据存储和处理元件的内容的电子设备。 该装置包括以并联装置连接的安全元件和相变元件。 安全元件是诸如常规晶体管或三端子相变装置的三端子装置,其具有关于电阻而不同的导通状态和截止状态,并且通过控制来调节对相变元件的电子接入 施加到并联组合的电流流动。 在ON状态下,安全元件的电阻小于相变元件的电阻,由此防止或混淆确定相变元件的电阻。 在该PROTECT模式下,确保相变元件的内容。 在OFF状态下,安全元件的电阻大于相变材料的电阻,使得并联组合的电阻接近相变元件的电阻。 在该READ模式中,可以确定相变元件的电阻和信息内容。 相变元件包括相变材料,优选为基于硫族化物的元件。 相变元件可以执行存储或处理功能,并且包括作为优​​选实施例的寄存器和加权设备。 ®KIPO&WIPO 2007
    • 2. 发明公开
    • 칼로겐화물 소자들을 위한 에러 감소 회로
    • 纠错装置的错误减少电路
    • KR1020070122200A
    • 2007-12-28
    • KR1020077021559
    • 2006-02-17
    • 에너지 컨버젼 디바이시즈, 아이엔씨.
    • 오브쉰스키스탠포드알.코헨모럴에이치.
    • H04L1/14H01P3/08
    • G11C13/0004
    • An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance. The error reduction circuit includes a network of chalcogenide devices, each of which is nominally equivalent and each of which is programmed into the same state having the same nominal resistance. The inclusion of multiple devices in the network of the instant error reduction circuit provides for a reduction in the contributions of both dynamic fluctuations and manufacturing fluctuations to the error in the output response.
    • 用于硫族化物存储器和计算设备阵列的误差减少电路。 误差降低电路减少与硫族化物器件的输出响应相关的误差。 在优选实施例中,输出响应是电阻,并且误差减小电路减小电阻的误差或波动。 误差减小电路包括一个硫族化物器件网络,其中每个器件名义上是等效的,并且每个都被编程成具有相同标称电阻的相同状态。 在瞬时误差减少电路的网络中包含多个设备提供了动态波动和制造波动对输出响应误差的贡献的降低。