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1. 发明授权

KR101636906B1 게이트 구동 장치 및 게이트 구동 방법 有权
标题翻译：门驱动装置及驱动门的方法
公开(公告)号：KR101636906B1
公开(公告)日：2016-07-07
申请号：KR1020090131298
申请日：2009-12-24
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 박재철 , 권기원 , 허지현 , 송이헌 , 김창정
IPC分类号： G09G3/36 , G09G3/20
摘要： 디스플레이장치의전력소비를감소시킬수 있는게이트구동장치및 게이트구동방법이개시된다. 개시된게이트구동장치및 게이트구동방법은, 이전의화소행을선택한후에다음의화소행을선택하는동안, 이전의화소행으로부터방전되는전류를다음의화소행에제공한다. 따라서, 이전의화소행에서버려지는전류를다음의화소행에서재활용할수 있으며, 각각의화소행을선택하기위하여필요한전류를감소시킬수 있다. 그결과, 개시된게이트구동장치및 게이트구동방법을채용한디스플레이장치는소비전력이전반적으로감소할수 있다.

2. 发明公开

KR1020110074361A 게이트 구동 장치 및 게이트 구동 방법 有权
标题翻译：门驱动装置和驱动门的方法
公开(公告)号：KR1020110074361A
公开(公告)日：2011-06-30
申请号：KR1020090131298
申请日：2009-12-24
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 박재철 , 권기원 , 허지현 , 송이헌 , 김창정
IPC分类号： G09G3/36 , G09G3/20
摘要： PURPOSE: A gate driving device and a gate driving method are provided to recycle a next pixel row by providing current discharged from a previous pixel row for the next pixel column. CONSTITUTION: A plurality of shifts(101,102,103,104) include a set signal input terminal, a first clock input terminal, a second clock input terminal, and an output terminal. A plurality of switches transfer the residual current discharged from each shift to the output of the other shift. A switch control unit(120) controls switching operations of a plurality of switches. A clock generator(110) generates a plurality of clocks to be inputted into the first clock input terminal and the second clock input terminal. The clock generator repeatedly generates sequentially three phase-shifted clock signals.
摘要翻译：目的：提供一种栅极驱动装置和栅极驱动方法，用于通过从下一像素列的先前像素行排出的电流来再循环下一个像素行。构成：多个位移（101,102,103,104）包括设定信号输入端子，第一时钟输入端子，第二时钟输入端子和输出端子。多个开关将从每个移位放电的剩余电流传送到另一个移位的输出。开关控制单元（120）控制多个开关的开关动作。时钟发生器（110）产生要输入到第一时钟输入端和第二时钟输入端的多个时钟。时钟发生器反复产生三个相移时钟信号。

3. 发明授权

KR101686582B1 유도결합 통신수단을 구비한 전자소자 有权
标题翻译：堆叠的电子设备在堆叠芯片之间具有感应耦合通信单元
公开(公告)号：KR101686582B1
公开(公告)日：2016-12-15
申请号：KR1020090129136
申请日：2009-12-22
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 송이헌 , 권기원 , 박재철
IPC分类号： H01L23/538
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： 유도결합통신수단을구비한전자소자가개시된다. 개시된유도결합통신수단을구비한전자소자는순차적으로적층된제1실리콘칩및 제2실리콘칩와, 상기제1실리콘칩상의제1인덕터및 상기제2실리콘칩상에서상기제1인덕터와대응되게배치되어상기제1인덕터와유도결합하는제2인덕터와, 상기제2실리콘칩에형성된관통홀;을구비한다. 기관통홀은상기제1인덕터에대응되게형성된다.
摘要翻译：目的：提供一种包括电感耦合通信单元的电子设备，通过减少涡流来稳定地发送和接收具有低功率的信号。构成：依次层叠第一硅芯片和第二硅芯片。第一电感器（112）布置在第一硅芯片上。第二电感器（122）布置在第二硅芯片上以对应于第一电感器并且与第一电感器感应耦合。穿孔（130）形成在第二硅芯片上，并包括与第一电感相对应的电感耦合通信单元。穿透孔形成在第二电感器中。绝缘体填充穿透孔。

4. 发明公开

KR1020100061290A 반도체 소자 및 그 제조방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020100061290A
公开(公告)日：2010-06-07
申请号：KR1020090038461
申请日：2009-04-30
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 박재철 , 송이헌 , 박영수 , 김창정 , 김경국 , 박성호 , 이성훈 , 김상욱 , 김선일 , 권기원
IPC分类号： H01L29/786
CPC分类号： H01L27/1225 , H01L27/092 , H01L27/1251
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a performance characteristic of the device by reducing a resistance with forming a p+ domain on the central part of a first oxide channel layer. CONSTITUTION: A first oxide channel layer(C10) is formed into a first conductive type oxide on a lower part layer. A first electrode layer covering the first channel layer is formed on the lower part layer. The first electrode layer and a second electrode layer separated are formed. A second oxide channel layer(C20) is formed into a second conductive type oxide on the lower part later. The first electrode layer is patterned. A first source, a first drain and the second drain are formed by the patterning of the first electrode layer.
摘要翻译：目的：提供半导体器件及其制造方法，以通过在第一氧化物沟道层的中心部分形成p +畴来降低电阻来提高器件的性能特性。构成：第一氧化物沟道层（C10）在下部层上形成为第一导电型氧化物。覆盖第一沟道层的第一电极层形成在下部层上。形成分离的第一电极层和第二电极层。第二氧化物沟道层（C20）稍后在下部形成第二导电型氧化物。图案化第一电极层。通过图案化第一电极层形成第一源极，第一漏极和第二漏极。

5. 发明公开

KR1020100040580A 적층 메모리 소자 无效
标题翻译：堆叠存储器件
公开(公告)号：KR1020100040580A
公开(公告)日：2010-04-20
申请号：KR1020080099778
申请日：2008-10-10
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 박재철 , 권기원 , 송이헌 , 박영수 , 김창정 , 김상욱 , 김선일
IPC分类号： H01L21/8239
CPC分类号： G11C5/02 , G11C5/143 , G11C7/18 , G11C8/12 , G11C13/0023 , G11C2213/71
摘要： PURPOSE: A stacked memory device is provided to reduce the area in which the stacked memory device is occupied by stacking active circuit parts between memory layers. CONSTITUTION: Stacked memory layers(110) include memory cell array. A first active circuit part(140) processes the address information of the memory cell array which is divided into vertical address information and horizontal address information. A second active circuit part(160) is arranged on the first active circuit part. The second active circuit part generates memory selection signal to each memory cell based on the processed signal of the first active circuit parts. The first active circuit part includes a level decoder(120) and a pre decoder(130). The level decoder decodes the vertical address information. The pre decoder decodes the horizontal address information.
摘要翻译：目的：提供堆叠的存储器件，以通过在存储器层之间堆叠有源电路部分来减少堆叠的存储器件被占用的区域。构成：堆叠的存储器层（110）包括存储单元阵列。第一有源电路部分（140）处理被划分为垂直地址信息和水平地址信息的存储单元阵列的地址信息。第二有源电路部分（160）布置在第一有源电路部分上。第二有源电路部分基于第一有源电路部分的处理信号，向每个存储器单元产生存储器选择信号。第一有源电路部分包括电平解码器（120）和预解码器（130）。电平解码器解码垂直地址信息。预解码器解码水平地址信息。

6. 发明公开

KR1020100038714A 비휘발성 메모리의 동작 방법 有权
标题翻译：非易失性存储器的操作方法
公开(公告)号：KR1020100038714A
公开(公告)日：2010-04-15
申请号：KR1020080097786
申请日：2008-10-06
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 안승언 , 권기원 , 박재철 , 박영수 , 이명재
IPC分类号： G11C16/34 , G11C16/08 , G11C16/10
CPC分类号： G11C8/06 , G06F12/0238 , G06F2212/7201 , G11C13/0069
摘要： PURPOSE: An operation method of a nonvolatile memory is provided to improve the reliability of a nonvolatile memory status by transiting the state of a nonvolatile memory to only one side direction. CONSTITUTION: The first logical address and the first physical address are written in the specific row of a look-up table(LUT). First data is programmed in data storage area which the first physical address points the first logical address(LA) is mapped. A first logical address and a second physical address(PA) are written in the other row of the look-up table. Second data is programmed in data storage area which the second physical address points.
摘要翻译：目的：提供一种非易失性存储器的操作方法，以通过将非易失性存储器的状态转换为仅一个侧面方向来提高非易失性存储器状态的可靠性。构成：第一个逻辑地址和第一个物理地址被写入查找表（LUT）的特定行。第一数据被编程在数据存储区域中，第一物理地址指向第一逻辑地址（LA）被映射。第一逻辑地址和第二物理地址（PA）被写入查找表的另一行。第二数据被编程在第二物理地址指向的数据存储区中。

7. 发明公开

KR1020090119666A 반도체소자 및 그 제조방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020090119666A
公开(公告)日：2009-11-19
申请号：KR1020080096027
申请日：2008-09-30
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 박재철 , 권기원
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/1251 , H01L29/66969 , H01L29/78621 , H01L29/78648 , H01L29/78696
摘要： PURPOSE: A semiconductor device and a method of manufacturing the same are provided to make manufacturing costs simple and reduce manufacturing costs by forming a source area and a drain area in plasma process. CONSTITUTION: In a semiconductor device and a method of manufacturing the same, a semiconductor device including a thin film transistor is composed of a first oxide semiconductor layer and a first lamination structure. The first oxide semiconductor layer is formed on the substrate(SUB1). The first oxide semiconductor layer has the first source areas between the first channel area and the first drain area. The first lamination structures include a first channel region where a first gate isolation layers and a first gate electrode which are sequentially laminated.
摘要翻译：目的：提供半导体器件及其制造方法，通过在等离子体工艺中形成源极区域和漏极区域，使制造成本简单并降低制造成本。构成：在半导体器件及其制造方法中，包括薄膜晶体管的半导体器件由第一氧化物半导体层和第一层叠结构构成。第一氧化物半导体层形成在基板（SUB1）上。第一氧化物半导体层具有在第一沟道区和第一漏区之间的第一源区。第一层叠结构包括第一沟道区，其中第一栅极隔离层和第一栅极电极依次层叠。

8. 发明授权

KR101416879B1 비휘발성 메모리의 동작 방법 有权
标题翻译：非易失性存储器的操作方法
公开(公告)号：KR101416879B1
公开(公告)日：2014-08-07
申请号：KR1020080097786
申请日：2008-10-06
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 안승언 , 권기원 , 박재철 , 박영수 , 이명재
IPC分类号： G11C16/34 , G11C16/08 , G11C16/10
CPC分类号： G11C8/06 , G06F12/0238 , G06F2212/7201 , G11C13/0069
摘要： 본 발명의 실시예에 따른 비휘발성 메모리의 동작 방법은, 통상적인 프로그래밍 동작에서는 비휘발성 메모리의 상태를 한쪽 방향으로만 천이시킨다.

9. 发明公开

KR1020110072278A 유도결합 통신수단을 구비한 전자소자 有权
标题翻译：堆叠式电池组合电感耦合器件的堆叠电子器件
公开(公告)号：KR1020110072278A
公开(公告)日：2011-06-29
申请号：KR1020090129136
申请日：2009-12-22
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 송이헌 , 권기원 , 박재철
IPC分类号： H01L23/538
CPC分类号： H01L2924/0002 , H01L23/538 , H01L2924/00
摘要： PURPOSE: An electronic device including an inductive coupling communication unit is provided to stably transmit and receive a signal with low power by reducing an eddy current. CONSTITUTION: A first silicon chip and a second silicon chip are successively laminated. A first inductor(112) is arranged on the first silicon chip. A second inductor(122) is arranged on the second silicon chip to correspond to the first inductor and is inductively coupled with the first inductor. A penetration hole(130) is formed on the second silicon chip and includes an inductive coupling communication unit to correspond to the first inductor. The penetration hole is formed in the second inductor. An insulator fills the penetration hole.
摘要翻译：目的：提供一种包括电感耦合通信单元的电子设备，通过减少涡流来稳定地发送和接收具有低功率的信号。构成：依次层叠第一硅芯片和第二硅芯片。第一电感器（112）布置在第一硅芯片上。第二电感器（122）布置在第二硅芯片上以对应于第一电感器并且与第一电感器感应耦合。穿孔（130）形成在第二硅芯片上，并包括与第一电感相对应的电感耦合通信单元。穿透孔形成在第二电感器中。绝缘体填充穿透孔。

10. 发明授权

KR100935936B1 적층 메모리 장치 有权
标题翻译：多层记忆装置
公开(公告)号：KR100935936B1
公开(公告)日：2010-01-11
申请号：KR1020080047092
申请日：2008-05-21
申请人： 삼성전자주식회사 , 성균관대학교산학협력단
发明人： 박재철 , 권기원 , 박영수 , 이승훈 , 안승언
IPC分类号： G11C17/00 , H01L21/8239 , H01L23/12
摘要： 본 발명은 적층 메모리 장치에 관한 것이다. 적층 메모리 장치에 있어서, 적층된 다수의 메모리층을 각각 포함하는 두 개 이상의 메모리부와 메모리부들 사이에 형성된 것으로, 디코더를 구비하는 적어도 하나의 능동회로부 포함하는 적층 메모리 장치를 제공한다.

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