专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

KR1020130104033A 저항성 메모리 장치 및 그것의 데이터 쓰기 방법 审中-实审
标题翻译：电阻式存储器件及其数据写入方法
公开(公告)号：KR1020130104033A
公开(公告)日：2013-09-25
申请号：KR1020120025160
申请日：2012-03-12
申请人： 삼성전자주식회사
发明人： 김대한 , 이천안
IPC分类号： G11C13/00 , G11C16/34
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/004 , G11C13/0064 , H01L27/249
摘要： PURPOSE: A resistive memory device and a data writing method thereof reduce the resistance distribution of a programmed memory cell by controlling the limited current according to a read resistance value of the memory cell while operating a program. CONSTITUTION: A resistive memory device includes a resistive memory cell and a reading and writing circuit (140). The reading and writing circuit programs reads out the resistive memory cell from a first state to a second state. The reading and writing circuit reads a resistance value of the resistive memory cell in the first state and controls the limited current provided to the resistive memory cell during a programming process according to the read resistance value.
摘要翻译：目的：电阻式存储器件及其数据写入方法通过在操作程序期间根据存储单元的读取电阻值控制限制电流来减小编程存储器单元的电阻分布。构成：电阻式存储器件包括电阻存储单元和读写电路（140）。读取和写入电路程序从第一状态读出电阻性存储器单元到第二状态。读取和写入电路在第一状态下读取电阻性存储单元的电阻值，并且根据读取的电阻值控制在编程处理期间提供给电阻性存储单元的限制电流。

2. 发明公开

KR1020130095959A 가변 저항 메모리 장치 및 그것의 구동 방법 审中-实审
标题翻译：可变电阻存储器件及其驱动方法
公开(公告)号：KR1020130095959A
公开(公告)日：2013-08-29
申请号：KR1020120017407
申请日：2012-02-21
申请人： 삼성전자주식회사
发明人： 이천안 , 곽동훈 , 백인규
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C2213/71 , G11C2213/77
摘要： PURPOSE: Variable resistance memory device and driving method thereof are provided to implement the high data integrity by blocking generation of disturbance due to leakage current without an optional device. CONSTITUTION: A level of access voltage is determined with reference to the number of column or row of cell arrays. The selected access voltage is supplied to the cell arrays. The access voltage is a program voltage (Vpgm) for changing a variable resistance memory cell into a reset state. The program voltage is the same or higher than the twice of a reset voltage (Vrst) in which the variable resistance memory cell starts to change to the reset state, that is, a high resistance state and is the same or lower than the reset voltage.
摘要翻译：目的：提供可变电阻存储器件及其驱动方法，通过在没有可选装置的情况下阻断由漏电流产生的干扰来实现高数据完整性。构成：参考电池阵列的列数或行数确定存取电压的电平。选择的存取电压被提供给单元阵列。存取电压是用于将可变电阻存储单元改变为复位状态的编程电压（Vpgm）。编程电压等于或高于可变电阻存储器单元开始变为复位状态的复位电压（Vrst）的两倍，即高电阻状态并且与复位电压相同或更低。

3. 发明授权

KR101942274B1 저항성 메모리 장치 有权
公开(公告)号：KR101942274B1
公开(公告)日：2019-01-28
申请号：KR1020120014425
申请日：2012-02-13
申请人： 삼성전자주식회사
发明人： 곽동훈 , 이천안
IPC分类号： G11C13/00 , G11C16/34 , G11C16/10

4. 发明授权

KR101868393B1 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 프로그램 방법 有权
公开(公告)号：KR101868393B1
公开(公告)日：2018-06-21
申请号：KR1020120026209
申请日：2012-03-14
申请人： 삼성전자주식회사
发明人： 김선아 , 곽동훈 , 이천안 , 이호철
IPC分类号： G11C16/10 , G11C16/08
CPC分类号： G11C16/10 , G11C8/08 , G11C16/0483
摘要： 본발명은불휘발성메모리장치의프로그램방법에관한것이다. 본발명의프로그램방법은, 복수의메모리셀들에연결된복수의워드라인들에음의전압을인가하는단계, 복수의워드라인들에패스전압을인가하는단계, 그리고복수의워드라인들중 선택된워드라인에프로그램전압을인가하는단계로구성된다.

5. 发明公开

KR1020110002178A ＤＲＡＭ의 비트라인 프리차지 회로 无效
标题翻译：用于预处理DRAM的电路的电路
公开(公告)号：KR1020110002178A
公开(公告)日：2011-01-07
申请号：KR1020090059635
申请日：2009-07-01
申请人： 삼성전자주식회사
发明人： 이천안 , 장성진 , 손종필 , 황상준
IPC分类号： G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4094
摘要： PURPOSE: A circuit for precharging the bit line of a DRAM is provided to remove the instability of a bit line voltage by supplying a voltage corresponding to a half of the power supply voltage to a bit line pair. CONSTITUTION: A plurality of switches(23-26) are connected between an output node outputting a bit line voltage and a power source. A plurality of capacitors(21, 22) are connected between two adjacent switches and a ground voltage. The voltage of an output node is precharged by a half of a power voltage according to each operation of the plural switches.
摘要翻译：目的：提供用于对DRAM的位线进行预充电的电路，以通过将对应于电源电压的一半的电压提供给位线对来消除位线电压的不稳定性。构成：多个开关（23-26）连接在输出位线电压的输出节点和电源之间。在两个相邻开关之间连接多个电容器（21,22）和接地电压。根据多个开关的每个操作，输出节点的电压被预充电一半的电源电压。

6. 发明授权

KR101996020B1 가변 저항 메모리 장치 및 그것의 쓰기 방법 有权
公开(公告)号：KR101996020B1
公开(公告)日：2019-07-04
申请号：KR1020120012928
申请日：2012-02-08
申请人： 삼성전자주식회사
发明人： 이천안 , 곽동훈
IPC分类号： G11C13/00 , G11C16/10

7. 发明授权

KR101948153B1 저항성 메모리 장치 및 그것의 데이터 쓰기 방법 有权
公开(公告)号：KR101948153B1
公开(公告)日：2019-02-14
申请号：KR1020120025160
申请日：2012-03-12
申请人： 삼성전자주식회사
发明人： 김대한 , 이천안
IPC分类号： G11C13/00 , G11C16/34

8. 发明公开

KR1020130091153A 반도체 메모리 장치 및 그 형성 방법 无效
标题翻译：半导体存储器件和制造器件
公开(公告)号：KR1020130091153A
公开(公告)日：2013-08-16
申请号：KR1020120012463
申请日：2012-02-07
申请人： 삼성전자주식회사
发明人： 박찬진 , 이천안 , 백인규
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/2463 , G11C16/0483 , H01L27/10882 , H01L27/2436
摘要： PURPOSE: A semiconductor memory device and a forming method thereof are provided to improve integration by arranging a semiconductor pattern between a first segment and a second segment. CONSTITUTION: A first segment includes a first memory element (150). The first memory element is interposed between first horizontal electrodes and first vertical electrodes. A second segment includes a second memory element (155). The second memory element is interposed between second horizontal electrodes and second vertical electrodes. A first semiconductor pattern (170) is arranged between the first and second segments.
摘要翻译：目的：提供半导体存储器件及其形成方法，以通过在第一段和第二段之间布置半导体图案来改善集成。构成：第一段包括第一存储元件（150）。第一存储元件介于第一水平电极和第一垂直电极之间。第二段包括第二存储元件（155）。第二存储元件介于第二水平电极和第二垂直电极之间。第一半导体图案（170）布置在第一和第二段之间。

9. 发明公开

KR1020100063294A 보호 회로를 구비하는 안티 퓨즈 회로 无效
标题翻译：具有保护电路的防冻电路
公开(公告)号：KR1020100063294A
公开(公告)日：2010-06-11
申请号：KR1020080121753
申请日：2008-12-03
申请人： 삼성전자주식회사
发明人： 장성진 , 이천안 , 신상웅
IPC分类号： G11C29/04 , G11C5/14 , G11C16/30
CPC分类号： G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE: An anti-fuse circuit is provided to easily execute repairing work after a package process by applying a program voltage by using a NC pin or a NC ball. CONSTITUTION: A protection circuit(10) is connected between a first pad and a common node. The protection circuit comprises a first protection part(11). An anti-fuse part(AFU1,AFU2) comprises an anti-fuse. The anti-fuse part programs the anti-fuse in response to a selection signal and a program mode signal. The anti-fuse part outputs each output signal according to the program state of the anti-fuse.
摘要翻译：目的：提供反熔丝电路，通过使用NC引脚或NC球应用编程电压，可以在封装过程之后轻松执行修复工作。构成：保护电路（10）连接在第一焊盘和公共节点之间。保护电路包括第一保护部分（11）。反熔丝部分（AFU1，AFU2）包括反熔丝。反熔丝部分响应于选择信号和编程模式信号编程反熔丝。反熔丝部分根据反熔丝的编程状态输出每个输出信号。

10. 发明授权

KR101929530B1 가변 저항 메모리 장치 및 그것의 구동 방법 有权
公开(公告)号：KR101929530B1
公开(公告)日：2019-03-15
申请号：KR1020120017407
申请日：2012-02-21
申请人： 삼성전자주식회사
发明人： 이천안 , 곽동훈 , 백인규
IPC分类号： G11C13/00

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式