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1. 发明授权

KR101362238B1 채널 추정기, 이를 포함하는 ＯＦＤＭ 수신기, 및 이의 동작 방법 有权
标题翻译：信道估计器，包括其的正交频分复用接收器及其操作方法
公开(公告)号：KR101362238B1
公开(公告)日：2014-02-13
申请号：KR1020120051843
申请日：2012-05-16
申请人： (주)아이앤씨테크놀로지
发明人： 이근무
IPC分类号： H04L27/26
摘要： 채널 추정기, 이를 포함하는 OFDM 수신기, 및 이의 동작 방법이 개신된다. 상기 채널 추정기는 프리앰블(preamble) 신호를 이용해 LS(least square) 채널 추정 방식에 의해 제1채널 상태 정보를 추정하고, 추정된 제1채널 상태 정보를 출력하는 LS 채널 추정 모듈, 상기 추정된 제1채널 상태 정보를 스무딩(smoothing)하고, 스무딩된 제1채널 상태 정보를 제2채널 상태 정보로서 출력하는 스무딩 채널 추정 모듈, 상기 프리앰블 신호 중에서 노이즈 성분의 크기와 상기 추정된 제1채널 상태 정보에 따라 선택 신호를 출력하는 컨트롤러, 및 상기 선택 신호에 응답하여 상기 추정된 제1채널 상태 정보 또는 상기 제2채널 상태 정보를 출력하는 선택기를 포함한다.

2. 发明授权

KR101360298B1 ＯＦＤＭ 통신 시스템에서 ＦＦＴ 윈도우 위치 결정 방법 및 ＯＦＤＭ 수신기 有权
标题翻译：在OFDM通信系统和OFDM接收机中确定FFT窗口的位置的方法
公开(公告)号：KR101360298B1
公开(公告)日：2014-02-12
申请号：KR1020120025133
申请日：2012-03-12
申请人： (주)아이앤씨테크놀로지
发明人： 황용석
IPC分类号： H04J11/00
摘要： OFDM 통신 시스템에서, OFDM 신호 내에 포함되고 보호 구간 및 데이터 구간을 포함하는 OFDM 심볼을 복원하기 위한 FFT 윈도우의 위치 결정 방법이 개시된다. 다중 경로 페이딩 채널을 통하여 전송된 상기 OFDM 신호에 기초하여, 다중 경로 페이딩 채널 중 최단 경로(first arrival path)에 상응하는 제1 위치 및 최장 경로(last arrival path)에 상응하는 제2 위치를 검출한다. 제1 위치, 제2 위치 및 보호 구간의 길이에 기초하여, 보호 구간 내에 포함되도록 상기 FFT 윈도우의 시작 위치를 설정한다.

3. 发明公开

KR1020130142422A 바이어스 전압 생성회로 有权
标题翻译：偏置电压发生电路
公开(公告)号：KR1020130142422A
公开(公告)日：2013-12-30
申请号：KR1020120065627
申请日：2012-06-19
申请人： (주)아이앤씨테크놀로지
发明人： 이정철
IPC分类号： G05F1/567 , G05F3/24
CPC分类号： G05F3/205 , G05F3/262 , G11C5/146 , G11C11/4074
摘要： The present invention introduces a bias voltage generation circuit for generating a bias voltage which has the minimum consumption area and the power consumption by using at least elements and adaptively varies depending on the process and temperature changes. The bias voltage generation circuit comprises a current source, a first MOS transistor to a third MOS transistor, and a MOS transistor for controlling a PTAT. The current source supplies a current of a certain size from the power connected to one terminal. The first MOS transistor has one terminal and a gate terminal which are connected to the other terminal of the current source. The MOS transistor for controlling the PTAT has one terminal which is connected to the other terminal of the first MOS transistor, the other terminal which is grounded and a gate to which a power voltage is applied. The second MOS transistor has one terminal which is grounded and a gate which is commonly connected to the gate of the first MOS transistor. The third MOS transistor has one terminal which is connected to the power and the other terminal and a gate which are connected to the other terminal of the second MOS transistor.
摘要翻译：本发明引入了一种偏置电压产生电路，用于通过使用至少元件产生具有最小消耗区域和功耗的偏置电压，并且根据工艺和温度变化自适应地变化。偏置电压产生电路包括电流源，第一MOS晶体管至第三MOS晶体管和用于控制PTAT的MOS晶体管。电流源从连接到一个终端的电源提供一定大小的电流。第一MOS晶体管具有连接到电流源的另一个端子的一个端子和栅极端子。用于控制PTAT的MOS晶体管具有一个端子，其连接到第一MOS晶体管的另一个端子，另一个端子接地，并且施加电源电压的栅极。第二MOS晶体管具有接地的一个端子和共同连接到第一MOS晶体管的栅极的栅极。第三MOS晶体管具有连接到电源的一个端子和连接到第二MOS晶体管的另一个端子的另一个端子和栅极。

4. 发明授权

KR101097373B1 하향 및 상향 주파수 변환기 有权
标题翻译：频率上/下变频器
公开(公告)号：KR101097373B1
公开(公告)日：2011-12-23
申请号：KR1020110050335
申请日：2011-05-26
申请人： (주)아이앤씨테크놀로지
发明人： 김영진 , 이진영 , 허수영 , 손성영 , 이상엽 , 이정훈 , 장신일
IPC分类号： H03D7/00
CPC分类号： H03D7/165 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0082
摘要： PURPOSE: A frequency up/down converter is provided to obtain the same frequency conversion performance even if the local oscillator signal with a low frequency is used by controlling the frequency signal of a conversion object during a cycle of the local oscillator signal at several times. CONSTITUTION: A frequency down conversion part(410) includes a first mixer(410A) and a second mixer(410B). A local oscillator signal generation part(420) includes a plurality of local oscillator signal generators(421-428). The first mixer includes a plurality of MOS(Metal Oxide Semiconductor) transistors which is connected in parallel to transfer a high frequency signal. The second mixer includes a plurality of MOS transistors which is connected in parallel to transfer the high frequency signal. The local oscillator signal generation part respectively supplies the local oscillator signal of a preset pulse width and phase to the gate of the MOS transistor which is connected in parallel.
摘要翻译：目的：提供频率上/下转换器以获得相同的频率转换性能，即使通过在本地振荡器信号的周期中多次控制转换对象的频率信号来使用低频本地振荡器信号。构成：降频转换部分（410）包括第一混频器（410A）和第二混频器（410B）。本地振荡器信号产生部分（420）包括多个本地振荡器信号发生器（421-428）。第一混频器包括并联连接以传送高频信号的多个MOS（金属氧化物半导体）晶体管。第二混频器包括并联连接以传送高频信号的多个MOS晶体管。本地振荡器信号产生部分分别将与预先设定的脉冲宽度和相位的本地振荡器信号并联连接到并联的MOS晶体管的栅极。

5. 发明授权

KR100402906B1 직교주파수분할다중방식에서의 주파수 오프셋 동기화 장치및 방법 有权
标题翻译： 직교주파수분할다중방식에서의주파수오프셋동기화장치및방직
公开(公告)号：KR100402906B1
公开(公告)日：2003-10-22
申请号：KR1020010006196
申请日：2001-02-08
申请人： 조용수 , (주)아이앤씨테크놀로지
发明人： 조용수 , 박경원
IPC分类号： H04L27/26
CPC分类号： H04L25/0232 , H04L25/0204 , H04L27/2659 , H04L27/266 , H04L27/2675 , H04L2025/03414 , H04L2025/03624
摘要： A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system includes a radio frequency (RF) receiving module for receiving OFDM signal, an analog/digital (A/D) converter connected to the RF receiving module, the A/D converter converting the OFDM signal into a digital signal, a frequency synchronization module connected to the A/D converter, the frequency synchronization module synchronizing carrier frequency, a Fast Fourier Transformer (FFT) connected to the frequency synchronization module, the FFT performing fast Fourier transformation to symbols from the frequency synchronization module, a channel estimation module connected to the FFT, the channel estimation module estimating channel response, an equalizer connected to the FFT and the channel estimation module, the equalizer equalizing channel, a residual phase tracking module connected to the equalizer, the residual phase tracking module tracking residual phase, a demodulator connected to the residual phase tracking module, the demodulator demodulating, and a controller connected to the frequency synchronization module, the controller controlling the frequency synchronization module.
摘要翻译：用于正交频分复用（OFDM）通信系统的频率同步装置包括用于接收OFDM信号的射频（RF）接收模块，连接到RF接收模块的模/数（A / D）转换器，A / D 将所述OFDM信号转换成数字信号的转换器，连接到所述A / D转换器的频率同步模块，所述频率同步模块同步载波频率，连接到所述频率同步模块的快速傅立叶变换器（FFT），所述FFT执行快速傅立叶变换来自频率同步模块的符号，连接到FFT的信道估计模块，信道估计模块估计信道响应，连接到FFT和信道估计模块的均衡器，均衡器均衡信道，连接到均衡器，残余相位跟踪模块跟踪残余相位，解调器连接到残余相位跟踪模块，解调器解调，以及连接到频率同步模块的控制器，控制器控制频率同步模块。

6. 发明授权

KR101520282B1 저잡음 증폭기의 집적회로 有权
标题翻译：低噪声放大器的集成电路
公开(公告)号：KR101520282B1
公开(公告)日：2015-05-15
申请号：KR1020140078940
申请日：2014-06-26
申请人： (주)아이앤씨테크놀로지
发明人： 장신일 , 장한용
IPC分类号： H03F1/26 , H03F3/24
CPC分类号： H03F1/26 , H01F27/2847 , H03F1/223 , H03F2200/372 , H03F2200/541 , H03F2200/543
摘要： 본발명은트랜스포머와교류차단용인덕터를구비하는집적화된저잡음증폭기의사이즈를줄이고, 양호도를향상시키는기술에관한것이다. 이러한본 발명은, 인덕터부, 상기인덕터부에대칭되게연결되는제1모스트랜지스터및 제2모스트랜지스터, 제1차권선이상기제2모스트랜지스터의타측단자와접지단자의사이에연결되고, 제2차권선이부하에연결된트랜스포머;를포함하되, 상기트랜스포머의제1차권선및 제2차권선의내측에상기인덕터부의인덕터들이나선형으로권취되어원주방향으로적층되는구조를갖는다.
摘要翻译：本发明涉及一种用于减小具有用于阻断AC和变压器的电感器并提高品质因数的集成低噪声放大器的尺寸的技术。本发明包括对称地连接到电感器par的电感器部分，第一MOS晶体管和第二MOS晶体管，具有连接在第二MOS晶体管的接地端子和端子之间的第一布线的变压器和第二布线连接到一个负载。电感器部分的电感器螺旋卷绕在变压器的第一布线和第二布线中，以在圆周方向上具有层压结构。

7. 发明授权

KR101444268B1 다중채널로 운영되는 무선통신 장비의 채널선택 장치 有权
标题翻译：用于选择多通道无线通信设备的通道的设备
公开(公告)号：KR101444268B1
公开(公告)日：2014-09-26
申请号：KR1020140037928
申请日：2014-03-31
申请人： (주)아이앤씨테크놀로지
发明人： 김동규 , 장한용
IPC分类号： H04W16/10
CPC分类号： H04W72/02 , H04W72/0486
摘要： The present invention relates to a technology of changing a use channel to another channel, in which a radar signal is not detected, when the radar signal is detected in a portion or an entire portion of the use channel in a wireless communication device managed through multiple channels. To this end, an apparatus for selecting a channel of a multi-channel based wireless communication device includes: a channel radar signal detection unit for detecting radar signals according to relevant frequency bands (channels) (e.g., 20 MHz of frequency bands) through a plurality of radar signal detection paths corresponding to a channel number used according to an operating bandwidth (Op-BW); a radar signal detection result processing unit for receiving the radar signal detection results from the channel radar signal detection unit to determine a channel of detecting the radar signal from among the Op-BW and for outputting the determination result accordingly; and a medium access controller for changing the Op-BW according to the determination result received from the radar signal detection result processing unit or for changing a presently-used channel into another channel after stopping a communication operation in the presently-used channel, thereby improving quality of service (QoS) of the multi-channel based wireless communication device.
摘要翻译：本发明涉及一种在通过多个管理的无线通信设备中在使用信道的部分或全部部分检测到雷达信号时，将使用信道改变为其中未检测到雷达信号的另一信道的技术通道。为此，用于选择基于多信道的无线通信设备的信道的装置包括：信道雷达信号检测单元，用于根据相关频带（信道）（例如，频带的20MHz），通过对应于根据工作带宽（Op-BW）使用的信道号的多个雷达信号检测路径; 雷达信号检测结果处理单元，用于接收来自信道雷达信号检测单元的雷达信号检测结果，以确定从Op-BW中检测雷达信号的信道，并相应地输出确定结果; 以及媒体接入控制器，用于根据从雷达信号检测结果处理单元接收到的确定结果来改变Op-BW，或者在停止当前使用的信道中的通信操作之后将当前使用的信道改变为另一信道，由此改善基于多信道的无线通信设备的服务质量（QoS）。

8. 发明授权

KR101438488B1 무선 랜 송신기의 송신전력 제어방법 有权
标题翻译：无线局域网发射机发射功率控制方法
公开(公告)号：KR101438488B1
公开(公告)日：2014-09-12
申请号：KR1020130048038
申请日：2013-04-30
申请人： (주)아이앤씨테크놀로지
发明人： 박배영 , 장한용
IPC分类号： H04W52/18 , H04W52/54
CPC分类号： H04W52/241 , H04W52/54 , H04W74/0816 , H04W84/12
摘要： The present invention relates to a technique for preventing power from being wasted and preventing the life of parts from being shortened by setting an optimized transmission power value using block acknowledgement frame information transmitted by a receiver when a wireless LAN transmitter using frame aggregation transmits frames. The present invention provides a method for controlling transmission power in the wireless LAN transmitter, comprising the steps of: measuring a received signal strength indication (RSSI) value and a signal to noise ratio (SNR) value from a received CTS frame, and calculating a frame power value to be currently transmitted based on previous frame power and power variation or setting a preset maximum power value as the frame power value to be currently transmitted, according to the measurement result; transmitting data coming down from an upper layer during session time obtained through an RTS frame and the CTS frame in a frame aggregate type, and checking whether a block acknowledgement frame is received from a wireless LAN receiver; and receiving the block acknowledgement frame from the wireless LAN receiver, calculating a frame error rate, and calculating the power variation for a frame to be transmitted in a next session, based on the calculated frame error rate.
摘要翻译：本发明涉及一种当使用帧聚合的无线LAN发送机发送帧时，通过使用由接收机发送的块确认帧信息来设定优化的发送功率值来防止功率被浪费并防止部件的寿命缩短的技术。本发明提供了一种用于控制无线LAN发射机中的发射功率的方法，包括以下步骤：从接收的CTS帧测量接收信号强度指示（RSSI）值和信噪比（SNR）值，并计算根据测量结果，基于先前的帧功率和功率变化当前发送的帧功率值或者将预设的最大功率值设置为当前发送的帧功率值; 在通过RTS帧和CTS帧以帧聚合类型获得的会话时间期间从上层发送数据，并且检查是否从无线LAN接收机接收到块确认帧; 以及基于所计算的帧错误率，从所述无线LAN接收器接收所述块确认帧，计算帧错误率，以及计算要在下一个会话中发送的帧的功率变化。

9. 发明授权

KR101334098B1 아날로그 IQ 교정회로 有权
标题翻译：模拟智能校准电路
公开(公告)号：KR101334098B1
公开(公告)日：2013-11-29
申请号：KR1020120065628
申请日：2012-06-19
申请人： (주)아이앤씨테크놀로지
发明人： 유정훈
IPC分类号： H03D3/02
摘要： The present invention discloses an analog IQ calibration circuit to perform analog IQ calibration using an analog circuit. The analog IQ calibration circuit performs individual calibration for an I-signal at the same phase as a signal to be transmitted or received and a Q-signal of which phase is different from the same of the I-signal at 90°. The analog IQ calibration circuit has a first VGA, a second VGA, and eight resistances.
摘要翻译：本发明公开了一种使用模拟电路进行模拟IQ校准的模拟IQ校准电路。模拟IQ校准电路对与要发送或接收的信号相同相位的I信号执行单独校准，并且在90度处与相位不同于I信号的Q信号进行单独校准。模拟IQ校准电路具有第一个VGA，第二个VGA和八个电阻。

10. 发明公开

KR1020090077413A 반도체 칩셋을 이용한 전자제품 불법복제 방지 방법 및장치 无效
标题翻译：用于电子产品复制保护的方法和装置与SEMICONDUCTOR CHIPSET
公开(公告)号：KR1020090077413A
公开(公告)日：2009-07-15
申请号：KR1020080003361
申请日：2008-01-11
申请人： (주)아이앤씨테크놀로지
发明人： 이종수
IPC分类号： G06F12/14 , H04L9/06 , G06F21/79 , G06F21/10
CPC分类号： G06F12/1408 , G06F21/10 , G06F21/79 , H04L9/0631
摘要： A method for preventing the illegal duplication of an electronic product by using a semiconductor chip set and an apparatus thereof are provided to prevent the firmware hacking of a central processing unit and the hacking performed through the decap of the semiconductor chip set. A developer program(101) generates a public key AP and a secret key AK, and encrypts the generated secret key AK through a secret key encryption algorithm. A central processing unit(102) executes the firmware, operates a public key encryption algorithm, and then finally determines whether a product is duplicated or not. A semiconductor chipset(103) has a flash memory to store the secret key decryption algorithm and public key decryption algorithm.
摘要翻译：提供一种通过使用半导体芯片组及其装置来防止电子产品的非法复制的方法，以防止中央处理单元的固件黑客入侵以及通过半导体芯片组的拆包执行的黑客攻击。开发者程序（101）生成公开密钥AP和秘密密钥AK，并通过秘密密钥加密算法加密生成的秘密密钥AK。中央处理单元（102）执行固件，操作公钥加密算法，然后最终确定产品是否被复制。半导体芯片组（103）具有存储秘密密钥解密算法和公开密钥解密算法的闪速存储器。

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