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1. 发明公开

KR20100109372A Page turning apparatus, booklet page turning method and id printer including the page turning apparatus 有权
标题翻译： PAGE TURNING APPARATUS，BOOKLET PAGE TURNING METHOD AND ID PRINTER INTRING THE PAGE TURNING APPARATUS
公开(公告)号：KR20100109372A
公开(公告)日：2010-10-08
申请号：KR20100019864
申请日：2010-03-05
申请人： TOSHIBA KK
发明人： ISHIOKA YUKINOBU
IPC分类号： B41J13/26 , B41F17/02 , B41J11/42 , B42D9/04
CPC分类号： B42D9/04 , B41J3/283 , B42D9/065 , B42D25/24
摘要： PURPOSE: A page turning device, a booklet page turning method, and an ID printer with the same are provided to reduce the movement of a vacuum pad, since the structure of a vacuum pad is formed inside a conveying design using buckling distortion. CONSTITUTION: A page turning device comprises a booklet conveying device(2a-2d), a pick-up sensor(19), drive units(21a,21b), a shaft, contact rollers(20A,20B), and a controller. The booklet conveying device sends booklets to a page turning location. The pick-up sensor detects the page of the booklet conveyed to the page turning location. The drive unit transfers a page pick-up unit in order to pick up the page of the booklet. The shaft contacts the page of the booklet.
摘要翻译：目的：提供翻页装置，小册子翻页方法和具有该打印机的ID打印机以减少真空垫的移动，因为真空垫的结构形成在使用屈曲变形的输送设计内。构成：翻页装置包括小册子传送装置（2a-2d），拾取传感器（19），驱动单元（21a，21b），轴，接触辊（20A，20B）和控制器。小册子传送装置将小册子发送到页面转动位置。拾取传感器检测到传送到页面转动位置的小册子的页面。驱动单元转移页面拾取单元，以便拾取小册子的页面。轴接触小册子的页面。

2. 发明公开

KR20100097044A Non-volatile semiconductor storage device 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：KR20100097044A
公开(公告)日：2010-09-02
申请号：KR20100016124
申请日：2010-02-23
申请人： TOSHIBA KK
发明人： HISHIDA TOMOO , IWATA YOSHIHISA , ITAGAKI KIYOTARO , MAEDA TAKASHI
IPC分类号： G11C16/02 , H01L27/115
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3454 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L27/0688
摘要： PURPOSE: A nonvolatile semiconductor storage device is provided to reduce time consumption by improving an erase operation required for writing-back data. CONSTITUTION: A control circuit includes an address decoder circuit(110), a word-line driving circuit(120), a selection gate line drive circuit(130), a first column decoder circuit(140), and the second column decoder circuit(150). The address decoder circuit outputs signals for specifying an column address. Signals are inputted to a first column decoder circuit and a second column decoder circuit. The word-line driving circuit outputs signals to the MB of each memory block.
摘要翻译：目的：提供一种非易失性半导体存储装置，通过改进回写数据所需的擦除操作来减少时间消耗。构成：控制电路包括地址解码器电路（110），字线驱动电路（120），选择栅极线驱动电路（130），第一列解码器电路（140）和第二列解码器电路 150）。地址解码器电路输出用于指定列地址的信号。信号被输入到第一列解码器电路和第二列解码器电路。字线驱动电路向每个存储块的MB输出信号。

3. 发明公开

KR20100094929A Valve unit and paper sheet takeout device 无效
标题翻译：阀门单元和纸张剥离器件
公开(公告)号：KR20100094929A
公开(公告)日：2010-08-27
申请号：KR20090081792
申请日：2009-09-01
申请人： TOSHIBA KK
发明人： TODORIKI TORU , MITSUYA YUSUKE , NARUOKA YOSHIHIKO
IPC分类号： B65H3/08 , B65H3/14 , B65H5/22
CPC分类号： B65H3/124 , B65H2406/412 , B65H2701/1916 , Y10T137/87249
摘要： PURPOSE: A valve unit and a paper taking out device, which circulates and blocks fluid of bulk at a high response speed, which is provided to precisely control the gap formed between papers. CONSTITUTION: A valve unit comprises a first member(21), a second member(23), a shielding plate(25) and a mobile unit(27). The first member comprises a first face and first holes facing with second fluid paths. The first hole is connected with a first flow path, and one end of the first hole is exposed toward the first face. The second member comprises a second face and second holes facing toward the space in the first face. The second hole is connected with a second flow path, and one end of the second hole is exposed toward the second face.
摘要翻译：目的：一种阀门单元和取纸装置，以高响应速度循环和阻止体积流体，以精确控制纸张之间形成的间隙。构成：阀单元包括第一构件（21），第二构件（23），屏蔽板（25）和移动单元（27）。第一构件包括面向第二流体路径的第一面和第一孔。第一孔与第一流路连接，第一孔的一端朝向第一面露出。第二构件包括面向第一面中的空间的第二面和第二孔。第二孔与第二流路连接，第二孔的一端朝第二面露出。

4. 发明公开

KR20090117934A MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：KR20090117934A
公开(公告)日：2009-11-16
申请号：KR20097018120
申请日：2009-03-03
申请人： TOSHIBA KK
发明人： NAGADOMI YASUSHI , TAKASHIMA DAISABURO , HATSUDA KOSUKE
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F11/1016 , G06F12/0246 , G06F2212/7203 , G06F2212/7209 , G11C16/102
摘要： A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data '0' of the read data has reached a preset criterion count number.
摘要翻译：一种存储系统（10），其包括具有多个存储单元的闪存EEPROM非易失性存储器（11），所述多个存储器单元具有浮动栅极，并且其中数据项是电可擦除和可写的;高速缓冲存储器（13），其临时存储闪存EEPROM非易失性存储器（11）的数据，控制闪存EEPROM非易失性存储器（11）和高速缓存存储器（13）的控制电路（12,14）以及与主机，其中控制电路用于从要被确定的闪存EEPROM非易失性存储器的期望目标区域读取数据，并且通过使用作为确定条件来检测擦除区域以确定写入区域/未写入区域读取数据的数据“0”的计数数已经达到预设的标准计数。

5. 发明公开

KR20070098674A SUBSTRATE TRANSFERRING APPARATUS, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD 审中-公开
标题翻译：基板传送装置，基板处理装置和基板处理方法
公开(公告)号：KR20070098674A
公开(公告)日：2007-10-05
申请号：KR20070030989
申请日：2007-03-29
申请人： TOKYO ELECTRON LTD , TOSHIBA KK
发明人： KOBAYASHI YOSHIYUKI , SAKAI ITSUKO , OHIWA TOKUHISA
IPC分类号： H01L21/677
CPC分类号： H01L21/67748 , H01L21/6831 , H01L21/6875 , H01L21/67742 , H01L21/68707 , Y10S414/141
摘要： A substrate transferring apparatus, a substrate processing apparatus, and a substrate processing method are provided to prevent physical contact between the substrate transferring apparatus and particles attached to a substrate. A substrate processing apparatus(1) includes a plurality of process ships(11) for subjecting a semiconductor device wafer(W) to reactive ion etching, and a loading unit(9) which is a rectangular-shaped common transfer chamber to which process ships(11) are connected. The loading unit(9) is connected to the process ships(11) and each of three FOUP mounting stages(15) with a FOUP(Front Opening Unified Pod)(14) that is a container for housing twenty-five wafers(W), and an orienter(16) to perform pre-alignment of the position of each wafer(W) transferred from the FOUP(14). A first sustaining unit is installed on a mounting stage to sustain a substrate to be processed. A second sustaining unit sustains a portion of the substrate different from a portion which is sustained by the first sustaining unit.
摘要翻译：提供了基板转印装置，基板处理装置和基板处理方法，以防止基板转印装置与附着到基板的颗粒之间的物理接触。基板处理装置（1）包括用于对半导体器件晶片（W）进行反应离子蚀刻的多个处理船（11）和作为矩形公共传送室的加载单元（9），处理船（11）连接。装载单元（9）通过FOUP（前开口统一座）（14）连接到处理船（11）和三个FOUP安装台（15）中的每一个，该FOUP（前开口统一座）（14）是用于容纳二十五个晶片（W）的容器和从FOUP（14）传送的每个晶片（W）的位置进行预对准的取向器（16）。第一维持单元安装在安装台上以维持待处理的基板。第二维持单元维持不同于由第一维持单元维持的部分的基板的一部分。

6. 发明公开

KR20180031760A 유로 구조 및 처리 장치 审中-公开
标题翻译：流程的结构和处理...
公开(公告)号：KR20180031760A
公开(公告)日：2018-03-28
申请号：KR20187005363
申请日：2017-06-26
申请人： TOSHIBA KK
发明人： HIGASHI SHINYA , TERADA TAKAHIRO , MATSUDA TAKUYA , KATO SHIGUMA , TANAKA MASAYUKI
IPC分类号： H01L21/67 , C23C16/455
CPC分类号： C23C16/455 , H01L21/31
摘要： 하나의실시형태에따른유로구조는, 하우징과, 복수의제1 벽부를구비한다. 상기하우징은, 제1 방향의단에위치하는외면을갖고, 내부에서로독립된두개의통로가설치되고, 당해두개의통로가각각, 적어도하나의유체실과, 상기외면에개구되는복수의개구와, 상기유체실에접속된복수의분기로를포함하고, 상기두개의통로각각의상기유체실이상기제1 방향으로교대로배치되어, 상기복수의분기로가상기복수의개구중 적어도하나와하나의상기유체실을접속하는상기복수의분기로및 하나의상기유체실과다른상기유체실을접속하는상기복수의분기로중 적어도한쪽을포함한다. 상기복수의제1 벽부는, 상기하우징에설치되고, 상기유체실에면하는동시에상기제1 방향으로상기유체실을개재하여배열된다.
摘要翻译：根据一个实施例的通道结构包括壳体和多个第一壁部分。其中壳体具有位于第一方向的端部处的外表面并且在其中设置有两个独立的通道，两个通道各自具有至少一个流体腔室，在外表面中的多个开口，并且多个分支通道连接到流体腔室，其中多个分支通道沿两个通道中的每一个通道的流体腔室故障底座1的方向交替布置，并且所述多个分支路径中的至少一个连接所述流体室和将所述一个流体室连接到另一个流体室的所述多个分支路径。多个第一壁部分设置在壳体中并且在面对流体室的同时沿第一方向布置在流体室中。

7. 发明公开

KR20120068357A Method of manufacturing semiconductor device 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR20120068357A
公开(公告)日：2012-06-27
申请号：KR20100129948
申请日：2010-12-17
申请人： TOSHIBA KK
发明人： SAWADA KANAKO , AOKI HIDEO , KOMUTA NAOYUKI , OGISO KOJI
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L2224/16225
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a void generated from a solder bump after melting by meting the solder bump. CONSTITUTION: A second substrate(4) having a second solder bump(3) is laminated on a first substrate(2) having a first solder bump(1). A laminate of the first substrate and the second substrate, in which the first solder bump and the second solder bump are temporarily fixed, is arranged in a furnace. The furnace in which the laminate is arranged has a decompression atmosphere inside thereof. A carboxylic acid gas is introduced into the furnace of the decompression atmosphere. Temperature inside the furnace rises to a temperature range over the melting temperature of the first and the second solder bumps and the first solder bump and the second solder bump are welded.
摘要翻译：目的：提供一种用于制造半导体器件的方法，以防止通过焊接凸块熔化之后由焊料凸块产生的空隙。构成：具有第二焊料凸点（3）的第二基板（4）层叠在具有第一焊料凸块（1）的第一基板（2）上。将第一焊料凸块和第二焊料凸块暂时固定的第一基板和第二基板的层叠体配置在炉中。配置有层叠体的炉子在其内部具有减压气氛。将羧酸气体引入减压气氛的炉中。炉内的温度上升到超过第一和第二焊料凸块的熔化温度的温度范围，并且焊接第一焊料凸块和第二焊料凸块。

8. 发明公开

KR20100106912A Method of manufacturing nonvolatile memory device 无效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：KR20100106912A
公开(公告)日：2010-10-04
申请号：KR20100020842
申请日：2010-03-09
申请人： TOSHIBA KK
发明人： TANAKA TOSHIHARU
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/24 , H01L27/2463 , H01L21/02362 , H01L21/28052 , H01L21/31051 , H01L45/04
摘要： PURPOSE: A non-volatile memory device manufacturing method is provided to prevent the collapse of the memory cells by forming a low aspect ratio which is the ratio of width to depth of a groove during manufacturing process. CONSTITUTION: A bit line corresponds to a first wire(11). A word line corresponds to a second wire(31). A third interlayer insulation layer is formed by interposing a second interlayer insulation layer(20) on a first interlayer insulation layer(10). A diode layer(21) is made of the material having the rectifying property.
摘要翻译：目的：提供一种非易失性存储器件制造方法，以通过在制造过程中形成作为沟槽的宽度与深度的比率的低纵横比来防止存储单元的崩溃。构成：位线对应于第一线（11）。字线对应于第二线（31）。通过在第一层间绝缘层（10）上插入第二层间绝缘层（20）来形成第三层间绝缘层。二极管层（21）由具有整流特性的材料制成。

9. 发明公开

KR20100084482A Nonvotile semiconductor memory and manufacturing method thereof 无效
标题翻译：非线性半导体存储器及其制造方法
公开(公告)号：KR20100084482A
公开(公告)日：2010-07-26
申请号：KR20100003803
申请日：2010-01-15
申请人： TOSHIBA KK
发明人： YAMAMOTO KAZUHIKO , YAHIRO KAZUYUKI , NAKAI TSUKASA
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L45/12 , H01L27/2409 , H01L27/2463 , H01L45/065 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , G11C13/0004
摘要： PURPOSE: A non-volatile semiconductor memory and a method for manufacturing the same are provided to prevent the combination of hydrogen of a resistance-change film and oxygen of a lower electrode by arranging a buffer layer, which is a nitrogen-doped carbon film, between the resistance-change film and the lower electrode. CONSTITUTION: A lower electrode(12) is formed on a substrate(11). A first buffer layer(13) is formed on the lower electrode. The first buffer layer is based on carbon. The first buffer layer further comprises nitrogen. A resistance-change film is formed on the first buffer layer. A second buffer layer is formed on the resistance-change film. An upper electrode(16) is formed on the second buffer layer.
摘要翻译：目的：提供一种非挥发性半导体存储器及其制造方法，以通过设置作为氮掺杂碳膜的缓冲层来防止电阻变化膜的氢与下部电极的氧的组合，在电阻变化膜和下电极之间。构成：在基板（11）上形成下电极（12）。第一缓冲层（13）形成在下电极上。第一缓冲层基于碳。第一缓冲层还包含氮气。在第一缓冲层上形成电阻变化膜。在电阻变化膜上形成第二缓冲层。在第二缓冲层上形成上电极（16）。

10. 发明公开

KR20080092290A SEMICONDUCTOR MEMORY DEVICE 无效
标题翻译：半导体存储器件
公开(公告)号：KR20080092290A
公开(公告)日：2008-10-15
申请号：KR20080033304
申请日：2008-04-10
申请人： TOSHIBA KK
发明人： MIZUKAMI MAKOTO , NISHIHARA KIYOHITO
IPC分类号： H01L27/115
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/11529 , H01L27/11531 , H01L27/11556 , H01L27/2463
摘要： A semiconductor memory device is provided to obtain high density of the device and lessen the number of contacts and the wires which are used to connect a gate wiring stacked structure with peripheral circuits by forming first and second interconnection layers in a memory cell array. A semiconductor memory device comprises a substrate(13), a memory cell array, and a peripheral circuit(12-1). The substrate has a step including a first upper surface and a second upper surface higher than the first upper surface. The memory cell array is formed on the first upper surface. The peripheral circuit is formed on the second upper surface and is configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure(15) having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction, and the second interconnection layers extend upward and are separated from each other by insulating films.
摘要翻译：提供半导体存储器件以通过在存储单元阵列中形成第一和第二互连层来获得高密度的器件并减少用于将栅极布线层叠结构与外围电路连接的接触数和导线数。半导体存储器件包括衬底（13），存储单元阵列和外围电路（12-1）。基板具有包括比第一上表面高的第一上表面和第二上表面的台阶。存储单元阵列形成在第一上表面上。外围电路形成在第二上表面上，并被配置为向存储单元阵列提供电信号。存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构（15）。第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并且在第一方向上延伸，并且第二互连层向上延伸并且通过绝缘膜彼此分离。

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