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81. 发明公开

KR1020090038818A 시험장치 失效
标题翻译：测验设备
公开(公告)号：KR1020090038818A
公开(公告)日：2009-04-21
申请号：KR1020080100673
申请日：2008-10-14
申请人： 가부시키가이샤 어드밴티스트
发明人： 코지마,쇼지
IPC分类号： G01R31/28
CPC分类号： G01R31/31924 , G11C29/56 , G11C2029/5602
摘要： A test equipment is provided to allow the amplitude of a difference signal fro DUT without input voltage of a first and a second amplifier by installing two replica drive amplifier. Automatic test equipment is connected with a DUT and a differential transmission line and output a differential signal from DUT. The DUT is composed of a sending amp, a receiving amp, and an output resistance(Rtu1,Rtu2). The receiving amp produces a differential voltage of the differential signal interposing the differential transmission line. A differential transmission line and the differential signal outputted from a transmit amplifier is inputted to ATE.
摘要翻译：提供了一种测试设备，通过安装两个副本驱动放大器来允许通过第一和第二放大器的输入电压的DUT的差分信号的幅度。自动测试设备与DUT和差分传输线相连，并从DUT输出差分信号。 DUT由发送放大器，接收放大器和输出电阻（Rtu1，Rtu2）组成。接收放大器产生插入差分传输线的差分信号的差分电压。将差分传输线路和从发送放大器输出的差分信号输入到ATE。

82. 发明授权

KR100883735B1 반도체메모리 시험장치 및 불량해석용 어드레스 발생기 失效
标题翻译：半导体存储器和地址分析仪的故障分析测试装置
公开(公告)号：KR100883735B1
公开(公告)日：2009-02-13
申请号：KR1020020071283
申请日：2002-11-15
申请人： 가부시키가이샤 어드밴티스트
发明人： 야마네도모유키
IPC分类号： G11C29/00
摘要： 버스(burst)기능을 가지는 메모리 디바이스(memory device)가 뱅크(bank)사이 인터리브(interleave)동작시의 시험을 하기위한 불량해석 메모리에 입력하는 어드레스(address)를 용이하게 발생시키는 반도체 메모리 시험장치에 관한 것으로서, 시험대상의 메모리 디바이스(DUT)의 각 뱅크에 대응하는 각 레지스터에 대응하는 뱅크의 행어드레스를 유지하고, 어느 한 뱅크의 개시 열어드레스가 DUT에 입력될때 그의 개시 열어드레스와 동일한 뱅크의 행어드레스를 그의 뱅크에 대응하는 레지스터로 부터 읽고, 그의 개시 열어드레스와 함께 불량해석 메모리에 출력하며, 또한 그의 뱅크의 버스트 동작중 그의 개시 열어드레스를 클럭 사이클 마다 연산해서 생성된 메모리 디바이스와 동일한 열어드레스와 함께 그의 행어드레스를 불량해석 메모리로 출력하는 것이 가능하다.

반도체 메모리 시험장치, 불량해석용 어드레스, 코맨드, 어드레스, 행어드레스, 열어드레스, 뱅크

83. 发明公开

KR1020080080645A 발진 회로, 시험 장치, 및 전자 디바이스 有权
标题翻译：振荡电路，测试装置和电子设备
公开(公告)号：KR1020080080645A
公开(公告)日：2008-09-04
申请号：KR1020087017484
申请日：2006-12-14
申请人： 가부시키가이샤 어드밴티스트
发明人： 수다마사카츠
IPC分类号： H03K3/03 , H03L7/099
CPC分类号： G01R31/31924 , G01R31/31926 , G01R31/31932 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K2005/00026 , H03L7/083 , H03L7/0995 , H03M9/00
摘要： An oscillation circuit which generates an oscillation signal synchronous with given reference clock. The oscillation circuit is provided with a voltage controlled oscillation section, which stops oscillation of an oscillation signal having a frequency corresponding to a given control voltage by having each edge of the reference clock as a trigger and starts new oscillation; a phase comparison section which compares the phase of a comparison signal having a phase corresponding to the oscillation signal outputted from the voltage controlled oscillation section with a phase of a signal having a phase corresponding to the reference clock; and a voltage control section which supplies the voltage controlled oscillation section with a control voltage corresponding to the comparison results obtained from the phase comparison section.
摘要翻译：产生与给定基准时钟同步的振荡信号的振荡电路。振荡电路设置有电压控制振荡部，通过使基准时钟的每个边缘作为触发并开始新的振荡，停止具有与给定控制电压对应的频率的振荡信号的振荡; 相位比较部，其将具有与从压控振荡部输出的振荡信号相对应的相位的比较信号的相位与具有与基准时钟相对应的相位的信号的相位进行比较; 以及电压控制部分，其向压控振荡部分提供与从相位比较部分获得的比较结果相对应的控制电压。

84. 发明公开

KR1020080070689A 시험장치, 픽쳐 보드 및 핀 일렉트로닉스 카드 失效
标题翻译：测试设备，固定板和PIN电子卡
公开(公告)号：KR1020080070689A
公开(公告)日：2008-07-30
申请号：KR1020087012491
申请日：2006-10-16
申请人： 가부시키가이샤 어드밴티스트
发明人： 와타나베다이스케
IPC分类号： G01R31/28 , H01L21/66
CPC分类号： G01R31/2889 , G01R31/31926 , G01R31/31928
摘要： Provided is a testing apparatus for testing devices to be tested which have a pre-emphasis circuit for emphasizing a prescribed component of an output signal and outputting it. The testing apparatus is provided with a filter for removing the emphasized component emphasized by the pre-emphasis circuit from an output signal outputted by the device to be tested, and a testing section for measuring the signal outputted from the filter and judges conformity of the device based on the measurement results. The testing apparatus can accurately test the pre-emphasis function of the device having the pre-emphasis circuit.
摘要翻译：提供了一种用于测试被测设备的测试装置，其具有用于强调输出信号的规定分量并将其输出的预加重电路。测试装置设置有滤波器，用于从由待测试装置输出的输出信号中去除由预加重电路强调的强调分量;以及测试部分，用于测量从滤波器输出的信号，并判断装置的一致性基于测量结果。测试装置可以准确地测试具有预加重电路的装置的预加重功能。

85. 发明授权

KR100838751B1 번인장치의 상태 진단방법 失效
标题翻译：诊断装置状态的方法
公开(公告)号：KR100838751B1
公开(公告)日：2008-06-17
申请号：KR1020067025717
申请日：2005-06-07
申请人： 가부시키가이샤 어드밴티스트
发明人： 기타가즈미 , 구라사와다다히로
IPC分类号： G01R31/3181 , G01R31/26
CPC分类号： G01R31/2872 , G01R31/2855 , G01R31/2868 , G01R35/00
摘要： 번인시험시에, 상기 번인시험을 행하는 각종 피측정 디바이스에 대하여 각각 히터 및 온도센서를 접촉시키고, 상기 히터의 소비전력을 제어하여 피측정 디바이스의 온도조정을 행하면서 상기 번인시험을 행하는 번인장치의 상태 진단방법에 있어서, 상기 피측정 디바이스와 히터 및 온도센서가 비접촉상태일 때, 이들 히터 및 온도센서가 배치됨과 동시에 냉각액이 접촉하는 온도 제어블록의 온도를 이 온도센서에 의하여 검출하고, 이 검출결과를 기초로 온도센서가 정상인지의 여부를 진단하도록 하고 있다.

86. 发明公开

KR1020080040712A 디바이스 식별 방법, 디바이스 제조 방법, 및 전자디바이스 失效
标题翻译：装置识别方法，装置制造方法和电子装置
公开(公告)号：KR1020080040712A
公开(公告)日：2008-05-08
申请号：KR1020087003696
申请日：2005-08-18
申请人： 가부시키가이샤 어드밴티스트 , 고쿠리츠 다이가쿠 호진 도호쿠 다이가쿠
发明人： 오카야스토시유키 , 스가와시게토시 , 테라모토아키노부
IPC分类号： H01L21/66 , H01L21/822 , H01L27/04
CPC分类号： H01L23/544 , G01R31/31718 , G11C2029/4402 , H01L21/76254 , H01L22/14 , H01L2223/5444 , H01L2924/0002 , Y10T29/49004 , H01L2924/00
摘要： Provided is a device identifying method for identifying an electronic device having an actually operating circuit which operates during actual operation of the electronic device and a testing circuit which has a plurality of testing elements and operates at the time of testing the electronic device. The device identifying method is provided with a characteristic measuring step wherein the electrical characteristics of the testing elements are measured; an identifying information storing step wherein the electrical characteristics of each of the testing elements are stored as identifying information of the electronic device; an identifying information acquiring step wherein the electrical characteristics of the testing elements included in the electronic device are measured so as to identify a desired electronic device, and the identifying information of the electronic device is acquired; and a matching step wherein the identifying information acquired in the identifying information acquiring step is compared with the identifying information stored in the identifying information storing step, and when the two kinds of identifying information match, the electronic devices are judged identical.
摘要翻译：提供了一种用于识别具有在电子设备的实际操作期间操作的实际操作电路的电子设备的设备识别方法和具有多个测试元件并且在测试电子设备时操作的测试电路。设备识别方法具有特征测量步骤，其中测量测试元件的电特性; 识别信息存储步骤，其中每个测试元件的电特性被存储为电子设备的识别信息; 识别信息获取步骤，其中测量包括在电子设备中的测试元件的电特性，以便识别期望的电子设备，并且获取电子设备的识别信息; 以及匹配步骤，其中将在所述识别信息获取步骤中获取的识别信息与存储在所述识别信息存储步骤中的识别信息进行比较，并且当所述两种识别信息匹配时，所述电子设备被判断为相同。

87. 发明公开

KR1020080040009A 타이밍 발생기, 시험 장치, 및 타이밍 발생 방법 失效
标题翻译：时序发生器，测试装置和时序生成方法
公开(公告)号：KR1020080040009A
公开(公告)日：2008-05-07
申请号：KR1020087006727
申请日：2006-08-24
申请人： 가부시키가이샤 어드밴티스트
发明人： 사토나오키
IPC分类号： G01R31/3183 , G01R31/28
CPC分类号： G01R31/31924 , G01R31/31922
摘要： A timing generator outputs a second-cycle signal having a desired phase difference from a first-cycle signal by superposing voltage on a control voltage of a voltage control oscillation unit of a PLL circuit generating the second-cycle signal. The timing generator includes an initialize unit for measuring a timing shift gain indicating the ratio of the timing shift amount against the change of the superposed voltage and a voltage generation unit for generating a superposed voltage according to the desired phase difference and the timing shift gain. The initialize unit matches the phase of the first-cycle signal with the phase of the second-cycle signal, successively changes the superposed voltage, detects a change amount of superposed voltage when the phase of the first-cycle signal coincides with the phase of the second-cycle signal again, and calculates the timing shift gain according to the change amount of the superposed voltage and the change amount of the phase of the second-cycle signal.
摘要翻译：定时发生器通过在产生第二周期信号的PLL电路的电压控制振荡单元的控制电压上叠加电压来输出具有来自第一周期信号的所需相位差的第二周期信号。定时发生器包括：初始化单元，用于测量指示时间偏移量与叠加电压变化的比率的定时偏移增益;以及用于根据期望的相位差和定时偏移增益产生叠加电压的电压产生单元。初始化单元将第一周期信号的相位与第二周期信号的相位相匹配，连续改变叠加电压，当第一周期信号的相位与第一周期信号的相位一致时，检测叠加电压的变化量并且根据叠加电压的变化量和第二周期信号的相位变化量来计算定时偏移增益。

88. 发明公开

KR1020080031137A 퍼포먼스 보드 및 커버 부재 有权
标题翻译：性能板和盖子成员
公开(公告)号：KR1020080031137A
公开(公告)日：2008-04-08
申请号：KR1020070099448
申请日：2007-10-02
申请人： 가부시키가이샤 어드밴티스트
发明人： 타케시타사토시
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G01R31/2874 , G01R31/2879
摘要： A performance board and a cover member are provided to shield heat applied from the outside by adding a heat-insulating property to the cover member. A performance board(200) is loaded into a semiconductor test apparatus(100) in order to mount a test target device. The performance board includes a substrate(500), a socket(510), and a cover member having a heat-insulating property. The socket is loaded on a surface of the substrate. The test target device is mounted in the socket. The cover member is loaded on a backside of the substrate corresponding to a socket installation region of the substrate. The performance board is loaded on a test head of the semiconductor test apparatus.
摘要翻译：提供了一种性能板和盖构件，用于通过向盖构件添加绝热性来屏蔽从外部施加的热。将性能板（200）装载到半导体测试装置（100）中以安装测试目标装置。性能板包括基板（500），插座（510）和具有绝热性能的盖构件。插座被装载在基板的表面上。测试目标设备安装在插座中。盖构件被装载在与衬底的插座安装区域相对应的衬底的背面上。性能板装载在半导体测试装置的测试头上。

89. 发明公开

KR1020080030046A 푸셔, 푸셔 유닛 및 반도체 시험 장치 无效
标题翻译：推杆，推杆单元和半导体测试装置
公开(公告)号：KR1020080030046A
公开(公告)日：2008-04-03
申请号：KR1020087001919
申请日：2005-07-21
申请人： 가부시키가이샤 어드밴티스트
发明人： 이토아키히코 , 야마시타츠요시 , 카나우미토모유키
IPC分类号： H01L21/66
CPC分类号： G01R31/2887 , G01R1/06705
摘要： A pusher (200) in a semiconductor testing apparatus (20) is provided for pressing a semiconductor device (300) to be tested toward a socket (500) for testing. The pusher is provided with a main body section (210) thermally connected to a heat source (400); and a plurality of device pressing sections (220), each of which is physically and thermally connected to the main body section (210), abuts to a plane of the semiconductor device (300) to be pressed, while being displaced toward the socket (500) by a pressing force from the main body section (210), presses the semiconductor device (300) and transmits heat from the heat source (400) to the semiconductor device (300). The pusher which improves heat conduction efficiency between the pusher and the semiconductor device to be tested, and performs accurate and quick semiconductor test is provided.
摘要翻译：提供半导体测试装置（20）中的推动器（200），用于将要测试的半导体器件（300）朝向插座（500）按压以进行测试。推动器设置有热连接到热源（400）的主体部分（210）。并且多个物理地和热连接到主体部分（210）的装置按压部分（220）邻近待挤压的半导体装置（300）的平面，同时朝向插座 500）通过来自主体部（210）的按压力按压半导体装置（300），并将热量从热源（400）传递到半导体装置（300）。提供了提高推进器和被测试的半导体器件之间的热传导效率并且执行准确且快速的半导体测试的推动器。

90. 发明公开

KR1020080007544A 시험 장치 및 시험 방법 无效
标题翻译：测试装置和测试方法
公开(公告)号：KR1020080007544A
公开(公告)日：2008-01-22
申请号：KR1020077020964
申请日：2007-03-22
申请人： 가부시키가이샤 어드밴티스트
发明人： 오자와타이키 , 사토신야
IPC分类号： G11C29/44 , G11C17/00 , G11C16/06 , G01R31/28
CPC分类号： G01R31/31932 , G11C29/56 , G11C29/56008 , G11C2029/5606
摘要： It is possible to effectively test a memory under test (hereinafter, referred to DUT) containing a data string having an error correction code. The test device compares each bit contained in the data string read from the DUT to an expectation value. The comparison result is stored as bit pass fail information indicating good/bad of each storage cell of the DUT in a first fail memory (hereinafter, referred to as FM). The storage device counts the number of bits which do not coincide with the expectation value for each page and judges whether the number of bits not coinciding with the expectation value satisfies the condition of the grade for each grade and page of the DUT. The judgment result is stored as page pass fail information indicating good/bad of each page for each grade in a second FM. If page pass fail information that a page containing a bit corresponding to a certain storage cell satisfies a certain grade condition is stored in the second FM, the test device modifies the bit pass fail information in the first FM to a value indicating that the storage fail is not bad and outputs it.
摘要翻译：可以有效地测试包含具有纠错码的数据串的被测存储器（以下称为DUT）。测试设备将从DUT读取的数据串中包含的每个位与期望值进行比较。将比较结果存储为在第一故障存储器（以下称为FM）中表示DUT的每个存储单元的良好/不良的位通过失败信息。存储装置对与每个页面的期望值不一致的比特数进行计数，并且判断与期望值不一致的比特数是否满足DUT的每个等级和页面的等级条件。判断结果作为页面通过失败信息存储，表示在第二个FM中每个档次的每个页面的好坏。如果在第二FM中存储了包含与特定存储单元相对应的位的页面的页面通过失败信息，则测试设备将第一FM中的位传递失败信息修改为指示存储失败的值不错，输出它。

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