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71. 发明公开

KR1020100079155A 트랜지스터 및 그 제조 방법 无效
标题翻译：晶体管及其形成方法
公开(公告)号：KR1020100079155A
公开(公告)日：2010-07-08
申请号：KR1020080137570
申请日：2008-12-30
申请人： 주식회사 디비하이텍
发明人： 최용건
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/42376 , H01L29/4925
摘要： PURPOSE: It improves the profile of the gate electrode and transistor and manufacturing method thereof improve the gap fill performance of the interlayer insulating film formed on the top. The generation of the void is prevented. CONSTITUTION: A layer of conductive material(105) is formed on the semiconductor substrate(101). A lattice damage layer(107) damaging lattice is formed about a part thickness of the layer of conductive material. The gate electrode having the level difference in the lattice damage layer and side the layer of conductive material is patterned is formed. The source/drain is formed based on the gate electrode within the semiconductor substrate of the either side.
摘要翻译：目的：改善栅电极和晶体管的轮廓，其制造方法提高了顶部形成的层间绝缘膜的间隙填充性能。防止空洞的产生。构成：在半导体衬底（101）上形成一层导电材料（105）。围绕导电材料层的部分厚度形成有损伤晶格的晶格损伤层（107）。形成具有晶格损伤层和导电材料层侧的电平差的栅电极。源极/漏极基于任一侧的半导体衬底内的栅电极形成。

72. 发明公开

KR1020100076675A ＰＭＯＳ 트랜지스터의 제조방법 失效
标题翻译：用于制造PMOS晶体管的方法
公开(公告)号：KR1020100076675A
公开(公告)日：2010-07-06
申请号：KR1020080134801
申请日：2008-12-26
申请人： 에스케이하이닉스 주식회사
发明人： 노경봉
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/66598 , H01L29/66659 , H01L29/7835 , H01L29/42376
摘要： PURPOSE: A manufacturing method of a PMOS transistor is provided to reduce the property weakness of a gate dielectric layer by forming an asymmetric dopant area on a semiconductor substrate by injecting the dopant in the state a poly silicone layer, the gate conductive layer is slope-etched. CONSTITUTION: A gate dielectric layer(110) and a poly silicone layer(130b) are formed on a semiconductor substrate(100). The poly silicone layer is slope-etched to a predetermined depth. The slop-etched poly silicone layer is doped with P-dopant. A hard mask(160) defining a domain in which the gate of the PMOS transistor is made, is formed on a gate metal layer(150). A gate stack is formed by patterning the gate metal layer, the poly silicone layer and the gate dielectric layer.
摘要翻译：目的：提供一种PMOS晶体管的制造方法，通过在聚硅氧烷层的状态下注入掺杂剂，在半导体衬底上形成不对称的掺杂剂区域来减小栅极电介质层的特性，蚀刻。构成：在半导体衬底（100）上形成栅介电层（110）和聚硅氧烷层（130b）。将聚硅氧烷层倾斜刻蚀至预定深度。斜面蚀刻的聚硅氧烷层掺杂有P掺杂剂。在栅极金属层（150）上形成限定形成PMOS晶体管的栅极的区域的硬掩模（160）。通过图案化栅极金属层，聚硅氧烷层和栅极电介质层来形成栅极堆叠。

73. 发明公开

KR1020100023573A 반도체 장치 및 그 제조방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020100023573A
公开(公告)日：2010-03-04
申请号：KR1020080082417
申请日：2008-08-22
申请人： 에스케이하이닉스 주식회사
发明人： 이병덕
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/66621 , H01L29/42376 , H01L29/66477 , H01L29/7831
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent a contact area reduction between a plug and a substrate by simultaneously forming a gate electrode and a plug. CONSTITUTION: A gate electrode(109) is formed on the top of a substrate(101). A plug is formed on the top of the substrate of both sides of the gate electrode and comprises a sidewall with a positive slope. A capping layer(105) is arranged between the gate electrode and the plug. A gate hard mask film(110) expands the sidewall on the gate electrode to the upper side of the capping layer. A recess pattern is formed under the gate electrode in the substrate. The sidewall of the capping layer has the negative slope.
摘要翻译：目的：提供半导体器件及其制造方法，以通过同时形成栅电极和插塞来防止插头和基板之间的接触面积减小。构成：在基板（101）的顶部上形成栅电极（109）。插塞形成在栅电极的两侧的基板的顶部上，并且包括具有正斜率的侧壁。封盖层（105）布置在栅电极和插塞之间。栅极硬掩模膜（110）将栅电极上的侧壁扩展到覆盖层的上侧。在基板的栅电极下方形成凹部图案。封盖层的侧壁具有负斜率。

74. 发明公开

KR1020090093390A 반도체 소자의 게이트 형성 방법 有权
标题翻译：制造半导体器件栅极的方法
公开(公告)号：KR1020090093390A
公开(公告)日：2009-09-02
申请号：KR1020080018893
申请日：2008-02-29
申请人： 전자부품연구원
发明人： 최홍구 , 한철구
IPC分类号： H01L29/778
CPC分类号： H01L29/42376 , H01L21/28587 , H01L29/66431
摘要： A method for manufacturing gate of semiconductor device is provided to observe easily a manufacturing state by forming firstly the leg part of T-gate. The first film(110) and the second film are formed in the upper side of an object(100). The second film is patterned and then the first film is exposed to form the first opening. The first film exposed to the first opening is removed to form the second opening. The second film is removed. Metal is deposited on the third film(130), and the second opening and the third opening(135). The first film is removed to form T-gate at the upper part of the object.
摘要翻译：提供一种用于制造半导体器件的栅极的方法，以便首先形成T形栅极的腿部来容易地观察制造状态。第一膜（110）和第二膜形成在物体（100）的上侧。将第二膜图案化，然后将第一膜暴露以形成第一开口。暴露于第一开口的第一膜被去除以形成第二开口。第二部电影被删除。金属沉积在第三膜（130）上，第二开口和第三开口（135）上。第一个胶片被去除，以在物体的上部形成T形门。

75. 发明公开

KR1020090071804A 고전압 반도체 소자 제조 방법 失效
标题翻译：制造高电压半导体器件的方法
公开(公告)号：KR1020090071804A
公开(公告)日：2009-07-02
申请号：KR1020070139706
申请日：2007-12-28
申请人： 주식회사 디비하이텍
发明人： 박동훈
IPC分类号： H01L29/78
CPC分类号： H01L29/42376 , H01L21/76801 , H01L21/8234
摘要： A manufacturing method of a high voltage semiconductor device is provided to prevent generation of void between gate patterns by functioning as blocking about a drift injection without thickness deposition of a gate poly. A gate oxide film(40) is formed on a semiconductor substrate(10). A gate poly(50) is formed on the gate oxide film. A blocking oxide film(60) is formed on the gate poly. A mask pattern is formed on the blocking oxide film. Etching about the blocking oxide film is performed by using the mask pattern. A hard mask pattern is formed from the blocking oxide film. A gate pattern is formed by performing etching about the gate poly after using the hard mask pattern.
摘要翻译：提供高电压半导体器件的制造方法，以防止在栅极聚合物的厚度沉积的情况下围绕漂移注入发生阻塞而产生栅极图案之间的空隙。在半导体衬底（10）上形成栅极氧化膜（40）。在栅极氧化膜上形成栅极（50）。在栅极聚合物上形成封闭氧化膜（60）。在阻挡氧化膜上形成掩模图案。通过使用掩模图案来进行阻挡氧化膜的蚀刻。由阻挡氧化膜形成硬掩模图案。在使用硬掩模图案之后，通过对栅极聚合物进行蚀刻来形成栅极图案。

76. 发明公开

KR1020090066911A 반도체 소자 및 그의 제조방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020090066911A
公开(公告)日：2009-06-24
申请号：KR1020070134656
申请日：2007-12-20
申请人： 에스케이하이닉스 주식회사
发明人： 천성길
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4236 , H01L21/76224 , H01L29/1037 , H01L29/42376 , H01L29/66621
摘要： A semiconductor device and a manufacturing method thereof are provided to minimize a change of characteristics of a transistor by minimizing an influence on a body. A semiconductor substrate(100) has an active area(C) in which a gate forming part is recessed. An isolation layer(102) is formed to limit the active area within the semiconductor substrate. A contact part between the isolation layer and the gate forming part is etched to protrude a bottom portion of the gate forming part in the recessed active area in a channel width direction. A gate(105) is recessed. The gate is formed on the gate forming part in the active area having the protruded bottom portion. A junction area(124,126) is formed within a surface of the active area in both sides of the gate.
摘要翻译：提供半导体器件及其制造方法，以通过最小化对体的影响来最小化晶体管的特性变化。半导体衬底（100）具有栅极形成部分凹入的有源区域（C）。形成隔离层（102）以限制半导体衬底内的有源区域。蚀刻隔离层和栅极形成部之间的接触部分，以使沟槽宽度方向上的凹入的有效区域中的栅极形成部分的底部突出。门（105）凹入。栅极形成在具有突出的底部的有源区域中的栅极形成部分上。连接区域（124,126）形成在门的两侧的有源区域的表面内。

77. 发明公开

KR1020090064657A 반도체 소자 失效
标题翻译：半导体器件
公开(公告)号：KR1020090064657A
公开(公告)日：2009-06-22
申请号：KR1020070131937
申请日：2007-12-17
申请人： 주식회사 디비하이텍
发明人： 조용수
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7831 , H01L29/42376 , H01L29/4983
摘要： A semiconductor device is provided to collect hot carriers moved to a gate electrode through a gate insulation film by arranging a parasitic gate in a side of the gate electrode. A gate electrode(200) is formed on a top part of a semiconductor substrate(100). A source region(410) and a drain region(420) are formed in both sides of the gate electrode. A pair of LDD(Lightly Doped Drain) regions(300) is isolated each other. A parasitic gate(600) is insulated with the gate electrode by a side insulation film(220). The parasitic gate is insulated with the drain region by a parasitic gate insulation film(230). The parasitic gate is formed on a top part of the drain region. A high electric field is formed in a channel region formed between the LDD regions by a high voltage applied to the source region. A hot carrier generated between the drain region and the channel region is collected by the parasitic gate.
摘要翻译：提供半导体器件以通过在栅电极的侧面布置寄生栅极来收集通过栅极绝缘膜移动到栅电极的热载流子。在半导体衬底（100）的顶部上形成栅电极（200）。源极区（410）和漏极区（420）形成在栅电极的两侧。一对LDD（轻掺杂漏极）区域（300）彼此隔离。寄生栅极（600）通过侧绝缘膜（220）与栅电极绝缘。寄生栅极通过寄生栅极绝缘膜（230）与漏极区绝缘。寄生栅极形成在漏区的顶部。通过施加到源极区域的高电压，在LDD区域之间形成的沟道区域中形成高电场。在漏极区域和沟道区域之间产生的热载流子由寄生栅极收集。

78. 发明授权

KR100902106B1 텅스텐함유막이 포함된 패턴을 구비한 반도체소자의 제조방법 失效
标题翻译：用于制造具有包括含钨膜的图案的半导体器件的方法
公开(公告)号：KR100902106B1
公开(公告)日：2009-06-09
申请号：KR1020070110347
申请日：2007-10-31
申请人： 에스케이하이닉스 주식회사
发明人： 성민규 , 양홍선 , 이태권 , 김원 , 임관용 , 이승룡
IPC分类号： H01L29/78
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/4941
摘要： 본 발명은 텅스텐함유막을 포함하는 패턴 제조 공정시 캡핑질화막 증착과 같은 후속 열공정에 의해 초래되는 리닝 현상을 방지할 수 있는 반도체소자의 제조 방법을 제공하기 위한 것으로, 본 발명의 반도체소자의 제조 방법은 텅스텐이 함유된 제1막을 포함하는 패턴을 형성하는 단계; 상기 패턴에 대해 질소를 포함하는 가스 분위기에서 프리퍼지(Pre-purge, 600∼700℃ 온도에서 1초∼5분동안 진행)를 진행하는 단계; 및 상기 패턴 상에 질소가 함유된 소스가스를 이용하여 제2막을 형성하는 단계를 포함하고, 본 발명은 후속 프리퍼지 공정시 시간을 짧게 하고 온도를 낮추므로써 텅스텐함유막의 W
2 N 반응을 억제할 수 있고, 이로써, W
2 N 반응에 의한 응력을 억제하여 패턴의 리닝현상을 방지할 수 있다.
텅스텐막, 게이트스택, 리닝, 응력, 프리퍼지, 질소
摘要翻译：本发明提供了一种制造半导体器件的方法，该方法能够防止在包括含钨膜的图案制造工艺中由诸如封盖氮化物膜沉积之类的随后的热处理引起的衬里现象，形成包含含钨的第一膜的图案; 在相对于图案的含有氮的气体气氛中进行预吹扫（在600至700℃下进行1秒至5分钟）; 并且使用图案上含有氮的源气体形成第二膜本发明涉及一种制造含钨膜的方法，

79. 发明公开

KR1020090045523A 반도체 소자의 리세스게이트 제조방법 无效
标题翻译：用于在半导体器件中制造记忆门的方法
公开(公告)号：KR1020090045523A
公开(公告)日：2009-05-08
申请号：KR1020070111387
申请日：2007-11-02
申请人： 에스케이하이닉스 주식회사
发明人： 오해순
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L29/1037 , H01L29/4236 , H01L29/42376
摘要： 본 발명은 리세스패턴 형성시 식각특성시 발생하는 첨점이 누설전류 포인트로 작용하는 것을 방지하기 위한 반도체 소자의 리세스게이트 제조방법을 제공하기 위한 것으로, 본 발명은 리세스패턴을 형성하는 단계; 상기 리세스패턴을 포함하는 기판 상에 게이트절연막을 형성하는 단계; 상기 리세스패턴의 어깨부에 첨점완화패턴을 형성하는 단계; 상기 게이트절연막 상에 상기 리세스패턴에 일부 매립되고 나머지는 기판 상부로 돌출되는 게이트패턴을 형성하는 단계를 포함하고, 리세스패턴 형성 후 단차피복성이 좋지않은 USG산화막을 추가로 형성하여 첨점을 완화시킴으로써 누설전류 포인트를 방지할 수 있는 효과가 있다.
첨점, 리세스패턴, 누설전류

80. 发明公开

KR1020090035771A 반도체 소자 및 그 제조방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020090035771A
公开(公告)日：2009-04-13
申请号：KR1020070100723
申请日：2007-10-08
申请人： 에스케이하이닉스 주식회사
发明人： 김호웅
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/28114 , H01L21/28123 , H01L29/42376
摘要： A semiconductor device and method for manufacturing the same is provided to increase the length of a channel by forming three-dimensional protrusion at a boundary area of an element isolation area and an active area. A gate pattern(29), a protrusion(21A), an active area(23), and an element isolation region(22) are formed on a substrate(21). The protrusion has a surface higher than the substrate at the edge of the active area contacting with the element isolation region under a gate pattern. The protrusion is composed of an active area contacting with the element isolation region or a substrate at the boundary of the element isolation region and the active region. The width(W2) of protrusion is smaller than the width(W1) of the gate pattern. The height of the protrusion at the edge of the active area contacting the element isolation under the gate pattern is higher than the width of the gate pattern to increase the length of the channel.
摘要翻译：通过在元件隔离区域和有源区域的边界区域形成三维突起来提供半导体器件及其制造方法，以增加通道的长度。在基板（21）上形成有栅极图案（29），突起（21A），有源区域（23）和元件隔离区域（22）。在栅极图案下，突起的表面高于与元件隔离区域接触的有源区域的边缘处的衬底。突起由与元件隔离区域接触的有源区域或元件隔离区域和有源区域的边界处的基板构成。突起的宽度（W2）小于栅极图案的宽度（W1）。在栅极图案下接触元件隔离的有源区域的边缘处的突起的高度高于栅极图案的宽度，以增加沟道的长度。

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