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71. 发明授权

KR100469964B1 고성능 알아이에스씨 마이크로프로세서 구조 失效
公开(公告)号：KR100469964B1
公开(公告)日：2005-02-11
申请号：KR1020037009653
申请日：1992-07-07
申请人： 세이코 엡슨 가부시키가이샤
发明人： 엥구엔레트롱 , 렌쯔데렉제이. , 미야야마요시유끼 , 가르그산지브 , 하기와라야스아끼 , 왕요하네스 , 라우테이-라이 , 트랑쿠앙에이취.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.

72. 发明授权

KR100449244B1 고성능 알아이에스씨 마이크로프로세서 구조 失效
公开(公告)号：KR100449244B1
公开(公告)日：2004-09-20
申请号：KR1020037009659
申请日：1992-07-07
申请人： 세이코 엡슨 가부시키가이샤
发明人： 엥구엔레트롱 , 렌쯔데렉제이. , 미야야마요시유끼 , 가르그산지브 , 하기와라야스아끼 , 왕요하네스 , 라우테이-라이 , 트랑쿠앙에이취.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.

73. 发明公开

KR1020040049254A 프로세서 내의 상태 정보 관리 방법, 프로세서 및 데이터처리 시스템 失效
标题翻译：用于在处理器中管理状态信息的方法和处理器，以及当处理中断被接收时通过节省软状态数据的数据处理系统
公开(公告)号：KR1020040049254A
公开(公告)日：2004-06-11
申请号：KR1020030077987
申请日：2003-11-05
申请人： 인터내셔널 비지네스 머신즈 코포레이션
发明人： 아리밀리라비쿠마 , 카그노니로버트알란 , 구드리가이린 , 스타크윌리엄존
IPC分类号： G06F9/22
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： PURPOSE: A method and a processor for managing state information in the processor, and a data processing system are provided to minimize a processing delay caused by storing and recovering an architected state in response to an interrupt. CONSTITUTION: The processor includes at least one executing unit(204), an ISU(Instruction Sequencing Unit)(202) combined to at least one executing unit, a cache(212), and interface circuit(216). The cache stores volatile information forming a part of soft state of a process. The interface transfers the soft state to a system memory(118a) by responding to process interrupt reception of the processor.
摘要翻译：目的：提供一种用于管理处理器中的状态信息的方法和处理器，并且提供数据处理系统以最小化响应于中断而存储和恢复架构状态所引起的处理延迟。构成：处理器包括至少一个执行单元（204），组合到至少一个执行单元的ISU（指令排序单元）（202），高速缓存（212）和接口电路（216）。高速缓存存储形成过程的软状态的一部分的易失性信息。接口通过响应处理器的处理中断接收将软状态传送到系统存储器（118a）。

74. 发明公开

KR1020040022436A 단일 스레드 프로그램의 암시적 멀티스레디드 실행을 행할수 있는 멀티스레디드 프로세서 有权
标题翻译：多线程处理器，能够执行单线程程序的隐式多线程执行
公开(公告)号：KR1020040022436A
公开(公告)日：2004-03-12
申请号：KR1020037016962
申请日：2002-06-14
申请人： 인텔 코포레이션
发明人： 아카리,하이탬 , 힐리,세바스티엔
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857
摘要： 제1 프로세서 및 제2 프로세서를 포함하는 디바이스가 개시된다. 다수의 메모리 디바이스가 제1 프로세서 및 제2 프로세서에 접속된다. 레지스터 버퍼가 제1 프로세서 및 제2 프로세서에 접속된다. 트레이스 버퍼가 제1 프로세서 및 제2 프로세서에 접속된다. 다수의 메모리 인스트럭션 버퍼가 제1 프로세서 및 제2 프로세서에 접속된다. 제1 프로세서 및 제2 프로세서는 멀티스레딩 자원을 이용하여 단일 스레드된 애플리케이션을 수행한다. 제1 스레드가 제2 프로세서로부터 실행되는 방법이 또한 개시된다. 제1 스레드는 또한 제1 프로세서에 의해 지시되는 바와 같이 제2 프로세서로부터 실행된다. 제2 프로세서는 제1 프로세서에 앞서서 인스트럭션을 실행한다.

75. 发明公开

KR1020040004506A 고성능 알아이에스씨 마이크로프로세서 구조 失效
公开(公告)号：KR1020040004506A
公开(公告)日：2004-01-13
申请号：KR1020037009657
申请日：1992-07-07
申请人： 세이코 엡슨 가부시키가이샤
发明人： 엥구엔레트롱 , 렌쯔데렉제이. , 미야야마요시유끼 , 가르그산지브 , 하기와라야스아끼 , 왕요하네스 , 라우테이-라이 , 트랑쿠앙에이취.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.

76. 发明公开

KR1020040004504A 고성능 알아이에스씨 마이크로프로세서 구조 失效
公开(公告)号：KR1020040004504A
公开(公告)日：2004-01-13
申请号：KR1020037009655
申请日：1992-07-07
申请人： 세이코 엡슨 가부시키가이샤
发明人： 엥구엔레트롱 , 렌쯔데렉제이. , 미야야마요시유끼 , 가르그산지브 , 하기와라야스아끼 , 왕요하네스 , 라우테이-라이 , 트랑쿠앙에이취.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.

77. 发明公开

KR1020040000410A 고성능 알아이에스씨 마이크로프로세서 구조 失效
公开(公告)号：KR1020040000410A
公开(公告)日：2004-01-03
申请号：KR1020037012158
申请日：1992-07-07
申请人： 세이코 엡슨 가부시키가이샤
发明人： 엥구엔레트롱 , 렌쯔데렉제이. , 미야야마요시유끼 , 가르그산지브 , 하기와라야스아끼 , 왕요하네스 , 라우테이-라이 , 트랑쿠앙에이취.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.

79. 发明授权

KR100335750B1 확장가능 알 아이 에스 씨(ＲＩＳＣ) 마이크로프로세서구조 失效
标题翻译：可扩展RISC微处理器架构
公开(公告)号：KR100335750B1
公开(公告)日：2002-05-09
申请号：KR1020017000941
申请日：1992-07-07
申请人： 세이코 엡슨 가부시키가이샤
发明人： 엥구엔레트롱 , 렌쯔데렉제이. , 미야야마요시유끼 , 가르그산지브 , 하기와라야스아끼 , 왕요하네스 , 라우테이-라이 , 트랑쿠앙에이취.
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： 고성능, RISC 코어기반마이크로프로세서구조는명령어스토어로부터명령어셋트를펫치하기위한명령어펫치유니트와, 기능유니트의병렬어레이를통해다수의명령어의동시실행을구현하는실행유니트를포함한다. 펫치유니트는일반적으로명령어버퍼내에소정수의명령어를유지한다. 실행유니트는상기명령어버퍼에결합되어실행을위한명령어를선택하기위한명령어선택유니트와, 명령어지정기능연산을수행하기위한다수의기능유니트를포함한다. 명령어선택유니트내의단일화된명령어스케쥴러는명령어가실행을위해이용가능한것으로결정되고그것에대해필요한계산기능을구현하는기능유니트중 적어도한 유니트가이용가능할때 기능유니트를통한명령어의처리를개시한다. 단일화된스케쥴링은복수의실행데이터경로를통해수행되는데, 각각의실행데이터경로, 및대응하는기능유니트는데이터에대해수행될계산기능의형태: 정수, 부동소수점및 부울에대해최적화된다. 각각의데이터경로및 그데이터경로사이에제공되는기능유니트의수, 형태및 계산적명세는서로독자적이다.

80. 发明授权

KR100267098B1 레지스터 파일 판독을 감소시키는 벡터 프로세서 디자인 失效
标题翻译：矢量处理器设计以减少寄存器文件读取端口
公开(公告)号：KR100267098B1
公开(公告)日：2000-10-02
申请号：KR1019970034998
申请日：1997-07-25
申请人： 삼성전자주식회사
发明人： 헌철박 , 성윤피터송
IPC分类号： G06F9/34
CPC分类号： G06F9/30018 , G06F9/30109 , G06F9/3013 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3885
摘要： PURPOSE: A vector processor design which decreases a register file reading is provided to implement a result forwarding operation and enhance a transfer speed based on an intelligent exploitation of a data dependency. CONSTITUTION: An instruction is fetched. The fetched instruction is decoded. A soft operand is read from a register file through a register file reading port in response to the number smaller than the number of the currently available register file reading ports or same as the same source operands and a value of a source operand irrespective of the previously executed instruction. The source operand is directly read based on the register file or a result of the previously executed instruction through the register file reading port after the source operand is updated and is used in the register file in response to the number smaller than the number of the currently available register file reading ports or same as the same source operands and a value of a source operand irrespective of the previously executed instruction. The fetched operand is applied to the fetched instruction for obtaining a result in the execution unit. The result is stored in the destination operand.
摘要翻译：目的：提供减少寄存器文件读取的向量处理器设计，以实现结果转发操作，并基于对数据依赖性的智能利用来提高传输速度。构成：提取指令。读取的指令被解码。响应于小于当前可用的寄存器文件读取端口的数量或与相同的源操作数相同的数量和源操作数的值，而不考虑先前的操作数，通过寄存器文件读取端口从寄存器文件读取软操作数执行指令。源操作数在源操作数更新之后，通过寄存器文件读取端口，基于寄存器文件或先前执行的指令的结果直接读取，并且响应于小于当前数目的数目在寄存器堆中使用源操作数可用的寄存器文件读取端口或相同的源操作数，以及源操作数的值，与先前执行的指令无关。获取的操作数被应用于获取的指令以在执行单元中获得结果。结果存储在目标操作数中。

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