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71. 发明授权

KR100935193B1 반도체 소자의 금속배선 및 그의 형성방법 失效
标题翻译：金属层半导体器件及其制造方法
公开(公告)号：KR100935193B1
公开(公告)日：2010-01-06
申请号：KR1020070065410
申请日：2007-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 김정태 , 염승진 , 김백만 , 이영진 , 정동하
IPC分类号： H01L21/28
摘要： 본 발명에 따른 반도체 소자의 금속배선은, 반도체 기판; 상기 반도체 기판 상에 형성되며, 다마신 패턴이 구비된 절연막; 상기 다마신 패턴의 표면 상에 형성되며, Ta 계열의 막과 질화물 계열의 막 사이에 TaN
y 막이 삽입된 구조를 갖는 확산방지막; 및 상기 확산방지막 상에 상기 다마신 패턴을 매립하도록 형성된 금속막;을 포함하는 것을 특징으로 한다.

72. 发明授权

KR100920040B1 반도체 소자의 배선 및 그의 형성방법 失效
标题翻译：半导体器件系列及其制造方法
公开(公告)号：KR100920040B1
公开(公告)日：2009-10-07
申请号：KR1020070063250
申请日：2007-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 염승진 , 김백만 , 이영진 , 정동하 , 김정태
IPC分类号： H01L21/3205 , H01L21/28
摘要： 본 발명에 따른 반도체 소자의 배선 및 그의 형성방법은, 다마신(Damascene) 패턴을 갖는 절연막과, 상기 다마신 패턴 내에 형성된 금속배선 및 상기 금속배선의 표면에 형성되고, CoReP의 물질로 이루어진 베리어막을 포함한다.

73. 发明授权

KR100914975B1 반도체 소자의 금속배선 형성방법 失效
标题翻译：形成半导体器件金属插头的方法
公开(公告)号：KR100914975B1
公开(公告)日：2009-09-02
申请号：KR1020060138497
申请日：2006-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 정동하 , 김백만 , 김수현 , 이영진 , 김정태
IPC分类号： H01L21/3205 , H01L21/28
摘要： 본 발명에 따른 반도체 소자의 금속배선 형성방법은, 반도체 기판 상에 콘택홀 및 트렌치를 갖는 절연막을 형성하는 단계와, 상기 콘택홀 및 트렌치 표면을 포함한 절연막 상에 TiB2막을 형성하는 단계와, 상기 TiB2막 상에 TiBN막을 형성해서 TiB2/TiBN의 베리어막을 형성하는 단계와, 상기 TiB2/TiBN의 베리어막 상에 콘택홀 및 트렌치를 매립하도록 알루미늄막을 형성하는 단계와, 상기 절연막이 노출되도록 알루미늄막과 TiB2/TiBN의 베리어막을 CMP하는 단계를 포함한다.

74. 发明公开

KR1020090075502A 반도체 소자의 금속배선 및 그 형성방법 失效
标题翻译：半导体器件的金属接线及其制造方法
公开(公告)号：KR1020090075502A
公开(公告)日：2009-07-08
申请号：KR1020080001379
申请日：2008-01-04
申请人： 에스케이하이닉스 주식회사
发明人： 정동하 , 염승진 , 김백만 , 김정태 , 이남열
IPC分类号： H01L21/28
CPC分类号： H01L21/76846 , H01L21/28556 , H01L21/76856 , H01L21/76871 , H01L21/76877
摘要： A metal wiring of a semiconductor device and a method of manufacturing the same are provided to prevent the diffusion of a cupper layer by forming a diffusion barrier with lamination structure of VB2 film and three components types of a V-B-N film. An insulating layer(102) is formed on a semiconductor substrate(100) while having a wring region(D). A diffusion barrier(108) comprises the laminate structure of a VB2 film(104) and three component types of V-B-N-film. A metal layer is formed in order to bury a region for the insulating layer on the diffusion barrier, and the VB2 film of the diffusion barrier has crystalline phase. A ternary phase film of the V-B-N of the diffusion barrier has the amorphous phase, and the seed layer(110) interposed between the diffusion barrier and metal layer is more included.
摘要翻译：提供半导体器件的金属布线及其制造方法，以通过形成具有VB2膜的叠层结构和V-B-N膜的三种组分类型的扩散阻挡层来防止铜层的扩散。在半导体衬底（100）上形成绝缘层（102），同时具有拧紧区域（D）。扩散阻挡层（108）包括VB2膜（104）的层叠结构和V-B-N膜的三种成分类型。形成金属层以便将绝缘层的区域埋在扩散阻挡层上，并且扩散阻挡层的VB2膜具有结晶相。扩散阻挡层的V-B-N的三元相膜具有非晶相，并且更多地包括介于扩散阻挡层和金属层之间的种子层（110）。

75. 发明公开

KR1020080114057A 반도체 소자의 배선 및 그의 형성방법 无效
标题翻译：半导体器件系列及其制造方法
公开(公告)号：KR1020080114057A
公开(公告)日：2008-12-31
申请号：KR1020070063249
申请日：2007-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 김정태 , 염승진 , 김백만 , 이영진 , 정동하
IPC分类号： H01L21/28
CPC分类号： H01L21/76846 , H01L21/76802 , H01L21/76856 , H01L21/76864 , H01L21/76877
摘要： A wiring of a semiconductor device and a method for forming the same are provided to reduce thickness of a diffusion barrier and improve a characteristic of the diffusion barrier by forming a first TiN layer with oxygen and a second TiN layer without oxygen as the diffusion barrier. A wiring of a semiconductor device includes metal wirings(104,124), and a diffusion barrier(122). The metal wiring is damascened by a predetermined pattern inside the insulating layer. The diffusion barrier is formed in a surface where the metal wiring is damascened. The diffusion barrier has a triple structure of a Ta series layer, a first TiN layer, and a second TiN layer.
摘要翻译：提供半导体器件的布线及其形成方法以通过形成具有氧的第一TiN层和没有氧的第二TiN层作为扩散阻挡层来减小扩散阻挡层的厚度并改善扩散阻挡层的特性。半导体器件的布线包括金属布线（104,124）和扩散阻挡层（122）。金属布线在绝缘层内部被预定的图案化。扩散阻挡层形成在金属布线被遮蔽的表面中。扩散阻挡层具有Ta串联层，第一TiN层和第二TiN层的三重结构。

76. 发明授权

KR100861306B1 반도체 소자의 배선 및 그의 형성방법 失效
标题翻译：半导体器件系列及其制造方法
公开(公告)号：KR100861306B1
公开(公告)日：2008-10-01
申请号：KR1020070063251
申请日：2007-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 정동하 , 염승진 , 김백만 , 이영진 , 김정태
IPC分类号： H01L21/28 , H01L21/283
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnection of a semiconductor device and a method for forming the same are provided to prevent the out-diffusion of metal components by using a Cr film as a diffusion barrier layer of a CrB2 and a seed layer of a metal line. An insulating layer(102) having a damascene pattern(D') is formed on a semiconductor substrate(100). A metal line(108) composed of a copper film is filled in the damascene pattern. A diffusion barrier layer(104) made of a CrB2 film is formed between the metal line and the insulating layer. A seed layer(106) is formed between the diffusion barrier layer and the metal line, and composed of a Cr film.
摘要翻译：提供半导体器件的互连及其形成方法，以通过使用Cr膜作为CrB 2的扩散阻挡层和金属线的种子层来防止金属成分的扩散。在半导体衬底（100）上形成具有镶嵌图案（D'）的绝缘层（102）。由铜膜构成的金属线（108）填充在镶嵌图案中。在金属线和绝缘层之间形成由CrB 2膜构成的扩散阻挡层（104）。种子层（106）形成在扩散阻挡层与金属线之间，由Cr膜构成。

77. 发明公开

KR1020080062578A 반도체 소자의 금속배선 형성방법 无效
标题翻译：形成金属互连层的半导体器件的方法
公开(公告)号：KR1020080062578A
公开(公告)日：2008-07-03
申请号：KR1020060138532
申请日：2006-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 김백만 , 신종한 , 김수현 , 이영진 , 정동하 , 김정태
IPC分类号： H01L21/28
CPC分类号： H01L21/76834 , H01L21/31111 , H01L21/76805 , H01L21/76877
摘要： A method for forming a metal wire of a semiconductor device is provided to prevent the corrosion of a lower metal wire by forming an etch stop layer on the lower metal wire to form a contact hole. An etch stop layer(306) is formed on a semiconductor substrate(300) where a lower metal wire(304) is formed. Interlayer dielectrics(302,308) are formed on the etch stop layer. The interlayer dielectrics are etched to expose the etch stop layer. The lower metal wire is exposed by etching the etch stop layer using an argon plasma process to form a contact hole(H'). The contact hole exposes the lower metal wire. A metal layer gap-fills the contact hole to form a metal plug. An upper metal wire(312) is formed on the metal plug. The upper metal wire is an aluminium layer. The lower metal wire is an aluminium layer. The etch stop layer is a silicon nitride layer. A thickness of the etch stop layer is 100 to 1000 Å.
摘要翻译：提供一种用于形成半导体器件的金属线的方法，以通过在下金属线上形成蚀刻停止层以形成接触孔来防止下金属线的腐蚀。在形成下金属线（304）的半导体衬底（300）上形成蚀刻停止层（306）。层间电介质（302,308）形成在蚀刻停止层上。蚀刻层间电介质以暴露蚀刻停止层。通过使用氩等离子体处理蚀刻蚀刻停止层来暴露下部金属线以形成接触孔（H'）。接触孔暴露下金属丝。金属层间隙填充接触孔以形成金属塞。在金属插头上形成上金属丝（312）。上金属线是铝层。下金属线是铝层。蚀刻停止层是氮化硅层。蚀刻停止层的厚度为100〜1000。

78. 发明公开

KR1020080061959A 반도체 소자의 금속배선 형성방법 无效
标题翻译：形成半导体器件金属插件的方法
公开(公告)号：KR1020080061959A
公开(公告)日：2008-07-03
申请号：KR1020060137174
申请日：2006-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 정동하 , 김백만 , 김수현 , 이영진 , 황선우 , 김정태
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L21/76846 , H01L21/7684 , H01L21/76877
摘要： A method for forming a metal line of a semiconductor device is provided to reduce Rs(resistance sheet) and to secure thickness uniformity of aluminum by preventing generation of TiAl3. An insulation layer having a contact hole(H) and a trench(T) is formed on a semiconductor substrate(400). A Ti-TiN layer(404) is formed as a diffusion barrier layer on the insulation layer. An aluminum layer(406,408) is formed on the diffusion barrier layer of the Ti-TiN layer to fill up the contact hole and the trench. The Ti-TiN diffusion barrier layer and the aluminum layer are planarized to expose the insulation layer. Wherein, the Ti-TiN layer is formed with the pure Ti on a portion bounded to the insulation layer, and with TiN satisfying the stochiometry on the portion bounded to the aluminum layer by gradually increasing the amount of nitrogen.
摘要翻译：提供了一种用于形成半导体器件的金属线的方法，以通过防止产生TiAl 3而减少Rs（电阻片）并确保铝的厚度均匀性。在半导体衬底（400）上形成具有接触孔（H）和沟槽（T）的绝缘层。在绝缘层上形成Ti-TiN层（404）作为扩散阻挡层。在Ti-TiN层的扩散阻挡层上形成铝层（406,408）以填充接触孔和沟槽。使Ti-TiN扩散阻挡层和铝层平坦化，使绝缘层露出。其中，Ti-TiN层在与绝缘层有界的部分上形成纯Ti，并且通过逐渐增加氮量，在满足铝层的部分上满足化学计量的TiN。

79. 发明公开

KR1020080057086A 반도체 소자의 비트 라인 제조 방법 无效
标题翻译：半导体器件位线的制造方法
公开(公告)号：KR1020080057086A
公开(公告)日：2008-06-24
申请号：KR1020060130418
申请日：2006-12-19
申请人： 에스케이하이닉스 주식회사
发明人： 김정태 , 김백만 , 김수현 , 이영진 , 황선우 , 정동하
IPC分类号： H01L21/28
CPC分类号： H01L21/76846 , H01L21/28556 , H01L21/76877 , H01L27/10885
摘要： A method for fabricating a bitline of a semiconductor device is provided to prevent a semiconductor substrate from being exposed to the atmosphere during a process for forming a bitline by forming a bitline composed of a tungsten silicide layer as an ohmic junction layer/a tungsten nitride layer as a diffusion barrier layer/a tungsten layer as a conductive layer by an ALD(atomic layer deposition) method. An interlayer dielectric(202) with a contact hole is formed on a semiconductor substrate(200) having an underlying structure. A pre-cleaning process can be performed on the surface of the semiconductor substrate. A tungsten silicide layer(204) as an ohmic junction layer, a tungsten nitride layer(206) as a diffusion barrier layer and a tungsten layer(208) as a conductive layer are continuously deposited on the interlayer dielectric in single equipment by an ALD process. The tungsten layer, the tungsten nitride layer and the tungsten silicide layer are etched to form a bitline in which the tungsten silicide layer, the tungsten nitride layer and the tungsten layer are incorporated.
摘要翻译：提供一种用于制造半导体器件的位线的方法，以防止在通过形成由硅化钨层组成的位线作为欧姆接合层/氮化钨层形成位线的过程期间半导体衬底暴露于大气中作为扩散阻挡层/通过ALD（原子层沉积）法作为导电层的钨层。具有接触孔的层间电介质（202）形成在具有下面结构的半导体衬底（200）上。可以在半导体衬底的表面上进行预清洁处理。作为欧姆结层的硅化钨层（204），作为扩散阻挡层的氮化钨层（206）和作为导电层的钨层（208）通过ALD工艺在单个设备中在层间电介质上连续沉积。蚀刻钨层，氮化钨层和硅化钨层，形成硅化钨层，氮化钨层和钨层的位线。

80. 发明公开

KR1020080002503A 반도체 소자의 게이트 및 그의 형성방법 无效
标题翻译：半导体器件的栅极及其形成方法
公开(公告)号：KR1020080002503A
公开(公告)日：2008-01-04
申请号：KR1020060061371
申请日：2006-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 곽노정 , 김백만 , 김수현 , 이영진 , 황선우
IPC分类号： H01L21/336
摘要： A gate of a semiconductor device is provided to avoid excessive loss of a gate by forming a stack layer of a nitride layer and an oxide layer as a hard mask for patterning the gate. A gate insulation layer(22) is formed on a semiconductor substrate(21). A gate conduction layer(25) is formed on the gate insulation layer. A hard mask layer(28) is formed on the gate conduction layer, made of a stack layer composed of a nitride layer(26) and an oxide layer(27). The nitride layer in the hard mask layer can have a thickness of 100~1000 Å. The oxide layer in the hard mask layer can have a thickness of 100~2000 Å.
摘要翻译：提供半导体器件的栅极，以通过形成氮化物层和氧化物层的堆叠层作为用于图案化栅极的硬掩模来避免栅极的过度损耗。在半导体衬底（21）上形成栅绝缘层（22）。栅极导电层（25）形成在栅极绝缘层上。在由氮化物层（26）和氧化物层（27）构成的堆叠层的栅极导通层上形成硬掩模层（28）。硬掩模层中的氮化物层可以具有100〜1000的厚度。硬掩模层中的氧化物层的厚度可以为100〜2000埃。

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