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61. 实用新型

KR200000960Y1 학습용 가승수 계산기 失效
公开(公告)号：KR200000960Y1
公开(公告)日：1960-03-25
申请号：KR2019590000106
申请日：1959-01-21
申请人： 박영수
发明人： 박영수
IPC分类号： G06F7/44

62. 发明授权

KR101590322B1 연산임계경로가 감소된 모듈러 곱셈기 및 연산임계경로 감소방법 有权
标题翻译：减少运行关键路径的模块化乘法器和减少运行关键路径的方法
公开(公告)号：KR101590322B1
公开(公告)日：2016-02-19
申请号：KR1020090042541
申请日：2009-05-15
申请人： 삼성전자주식회사
发明人： 김영식 , 노미정 , 안경문 , 신선수
IPC分类号： G06F7/52 , G06F7/44 , G06F7/00
CPC分类号： G06F7/728
摘要： 본발명은긴경로캐리값을예측하여몽고메리모듈러곱셈의연산임계경로가감소된모듈러곱셈기및 연산임계경로를감소시키는방법을개시한다. 상기모듈러곱셈기는, 모듈러스, 임의의 2 상수를이용하여모듈러곱셈의몫 및연산결과를구하는것으로, 감산기, 캐리예측기및 누산기를구비한다. 상기감산기는중간계산결과를이용하여현재단계의연산결과를구하는과정에포함되는짧은경로캐리를연산한다. 상기캐리예측기는중간계산결과를이용하여상기연산결과를구하는과정에포함되는긴경로캐리를예측한다. 상기누산기는상기짧은경로캐리및 상기긴경로캐리를이용하여상기현재단계의연산결과를축적시킨다. 상기중간계산결과는이전단계에서계산한연산결과및 현재단계에서계산된두 상수의부분곱을더한것이다.

63. 发明公开

KR1020140077701A 고속 세제곱 연산 모듈 审中-实审
标题翻译： GF（3M）快速操作员
公开(公告)号：KR1020140077701A
公开(公告)日：2014-06-24
申请号：KR1020120146779
申请日：2012-12-14
申请人： 한국전자통신연구원 , 고려대학교 산학협력단
发明人： 조남수 , 홍석희 , 권태웅
IPC分类号： G06F17/10 , G06F7/44
CPC分类号： G06F7/723 , G06F7/724
摘要： The present invention relates to a high-speed cube computation module. The high-speed cube computation module according to an embodiment of the present invention conducts cube computation which is the basis of the pairing encryption computation to accelerate the speed of the pairing encryption algorithm computation in a limited implementation environment such as a ubiquitous computing environment. When the cube computation module is implemented in a hardware or software environment, the cube computation module can shorten the time required for the cube computation as low as 1/7.
摘要翻译：本发明涉及一种高速立方体计算模块。根据本发明的实施例的高速立方体计算模块进行立方体计算，其是配对加密计算的基础，以在诸如无处不在的计算环境的有限实施环境中加速配对加密算法计算的速度。当立方体计算模块在硬件或软件环境中实现时，立方体计算模块可以将多维数据集计算所需的时间缩短到1/7。

64. 发明公开

KR1020120077177A ＳＩＭＤ 프로세서를 이용하는 갈로아 필드 이진 다항식 제산 장치 및 방법 有权
标题翻译：使用SIMD处理器对GALIOS场二进制多项式表达进行分割的方法和装置
公开(公告)号：KR1020120077177A
公开(公告)日：2012-07-10
申请号：KR1020100139042
申请日：2010-12-30
申请人： 삼성전자주식회사 , 광운대학교 산학협력단
发明人： 양호 , 이현석 , 방지훈 , 박영환 , 배기택 , 김경연
IPC分类号： G06F7/72 , G06F7/44 , G06F9/38 , G06F9/30
CPC分类号： G06F7/724 , G06F7/38 , G06F7/44 , G06F7/72 , G06F9/30 , G06F9/3001 , G06F9/38 , G06F9/3887
摘要： PURPOSE: A method and an apparatus for division of galios field binary polynomial expression using an SIMD(Single Instruction Multiple Data) processor are provided to implement binary polynomial division through parallel selective XOR computation. CONSTITUTION: XOR computation units(720,730,740,750) receive first and second input values and creates and outputs a value by selectively XOR-computing the first and second input values. First and second storage units(710,720) store first and second binary values. If the uppermost bit of the second input value is 1, the selective XOR computation produces the result of XOR computation of the first and second input values. If the upper most bit of the second input value is 0, the selective XOR computation produces the result of XOR computation of the second input value.
摘要翻译：目的：提供一种使用SIMD（单指令多数据）处理器对galios场二进制多项式表达进行分割的方法和装置，以通过并行选择性XOR计算实现二进制多项式除法。构成：XOR计算单元（720,730,740,750）接收第一和第二输入值，并通过选择性地XOR计算第一和第二输入值来创建和输出值。第一和第二存储单元（710,720）存储第一和第二二进制值。如果第二输入值的最高位为1，则选择性XOR计算产生第一和第二输入值的异或运算结果。如果第二输入值的最高位为0，则选择性XOR计算产生第二输入值的异或运算的结果。

65. 发明公开

KR1020100090751A 곱셈 기능을 수행하기 위한 방법 및 장치 有权
标题翻译：用于执行多项功能的方法和装置
公开(公告)号：KR1020100090751A
公开(公告)日：2010-08-17
申请号：KR1020100066205
申请日：2010-07-09
申请人： 인텔 코포레이션
发明人： 탕,핑택피터 , 캐빈,로버트디.
IPC分类号： G06F7/57 , G06F7/44 , G06F7/52
CPC分类号： G06F7/535 , G06F7/483 , G06F7/5443 , G06F2207/5354 , G06F2207/5356
摘要： PURPOSE: A method and an apparatus for performing multiplicative functions are provided to reduce standby time thereof by removing reciprocal calculation. CONSTITUTION: A computing system(100) comprises one or more processors(110) coupled to a system interconnect(115). The processor has multiple or many processing cores. The computing system also includes a chipset(130) coupled to the system interconnect. The chipset includes one or more integrated circuit packages or chips. Chipset comprises one or more device interfaces(135) to support data transfers to and/or from other components(160) of the computing system such as, for example, keyboards, mice, network interfaces, etc. The device interface is coupled with other components through a bus(165). The chipset is coupled to a PCI(Peripheral Component Interconnect) bus(185). The chipset includes a PCI bridge(145) that provides an interface to the PCI bus. The PCI Bridge provides a data path between the processor as well as other components, and peripheral devices such as, for example, an audio device(180). Other devices are also coupled to the PCI bus.
摘要翻译：目的：提供一种用于执行乘法函数的方法和装置，以通过去除相互计算来减少其待机时间。构成：计算系统（100）包括耦合到系统互连（115）的一个或多个处理器（110）。处理器具有多个或多个处理核心。计算系统还包括耦合到系统互连的芯片组（130）。芯片组包括一个或多个集成电路封装或芯片。芯片组包括一个或多个设备接口（135），以支持向计算系统的其他组件（160）传送数据和/或从计算系统的其他组件（160）传输数据，例如键盘，鼠标，网络接口等。设备接口与其他部件通过总线（165）。芯片组耦合到PCI（外围组件互连）总线（185）。该芯片组包括提供PCI总线接口的PCI桥（145）。 PCI桥提供处理器以及其他组件之间的数据路径，以及外围设备，例如音频设备（180）。其他设备也耦合到PCI总线。

66. 发明授权

KR100932033B1 복합 갈루아 필드 엔진과 갈루아 필드 나눗셈 및 제곱근엔진과 방법 有权
标题翻译： 복합갈루아필드엔진과갈루아필드나눗셈및제곱근엔진과방복합
公开(公告)号：KR100932033B1
公开(公告)日：2009-12-15
申请号：KR1020057021863
申请日：2004-03-29
申请人： 아나로그 디바이시즈 인코포레이티드
发明人： 스테인,요세프 , 카블로츠키,조슈아,에이.
IPC分类号： G06F7/44 , G06F7/38 , G06F7/00
CPC分类号： G06F7/726 , G06F7/552 , G06F2207/5523
摘要： A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in the Galois field reciprocal generator the first Galois field element by the output of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m−2 times to obtain the reciprocal of the first Galois field element, and multiplies the reciprocal element by a second Galois field element for predicting the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform.
摘要翻译：伽罗瓦域分频器引擎和方法将1和第一伽罗瓦域单元输入到伽罗瓦域互易发生器以获得输出，将伽罗瓦域互易发生器中的第一伽罗瓦域单元与伽罗瓦域互逆发生器的输出相乘以用于预测为了得到第一伽罗瓦域元素的倒数，将不可约多项式m＆amp; - 减去2次的多项式乘积的平方的模余数，并将该倒数元素与第二伽罗瓦域元素相乘以预测两个伽罗瓦的商 m个周期中的场元素; 在更广泛的意义上，本发明包括用于在一系列多项式输入上执行连续的伽罗瓦域线性变换以获得最终输出的复合伽罗瓦域引擎，其中除第一输入之外的每个输入是先前伽罗瓦域线性变换的输出。

67. 发明公开

KR1020090059921A 모듈러 곱셈 장치 및 그 방법 有权
标题翻译：模块化乘法器的装置和方法
公开(公告)号：KR1020090059921A
公开(公告)日：2009-06-11
申请号：KR1020070127020
申请日：2007-12-07
申请人： 한국전자통신연구원
发明人： 김영세 , 김무섭 , 박지만 , 박영수 , 전성익
IPC分类号： G06F7/52 , G06F7/44
CPC分类号： G06F7/722 , G06F7/507 , G06F7/728
摘要： A modular multiplier and a method thereof are provided to control a memory directly while continuously performing word-base modular multiplication process. A modular multiplying unit(220) repetitively performs a modular multiplication operation. A memory(230) stores one or more return values generated during the operation process. A modular interface unit(210) is synchronized with the modular multiplying unit by using one of the return values, stores values outputted from the multiplying unit in the memory, and then reads at least one value requested by the multiplying unit from the memory to provide the read result to the multiplying unit.
摘要翻译：提供了一种模数乘法器及其方法，用于直接控制存储器，同时连续执行字库模乘法。模块化乘法单元（220）重复执行模乘法。存储器（230）存储在操作处理期间生成的一个或多个返回值。模块化接口单元（210）通过使用返回值中的一个与模块化乘法单元同步，将从乘法单元输出的值存储在存储器中，然后从存储器读取由乘法器请求的至少一个值，以提供读取结果到乘法单元。

68. 发明公开

KR1020080052145A 나눗셈기의 평균값 출력 장치 및 출력 방법 失效
标题翻译：输出装置和平均值生成方法
公开(公告)号：KR1020080052145A
公开(公告)日：2008-06-11
申请号：KR1020070031691
申请日：2007-03-30
申请人： 한국전자통신연구원
发明人： 조성철 , 김형진 , 조권도 , 김진업 , 김대식
IPC分类号： G06F7/44 , G06F7/00
CPC分类号： G06F7/544
摘要： An apparatus and a method for outputting a mean value in a dividing operator are provided to minimize a quantization error in the operation, to perform a simple shift operation for having a minimized quantization error, to determine the round-off just through recognizing whether the least significant bit is "0", and thereby to achieve high operational speed. A method for outputting a mean value in a dividing operator comprises the following several steps. A counter counts number of times the data are input and sends a counting result to an address generation unit(S1). An adder performs an addition operation on the inputted data each time the data are input, and sends a result of the addition operation to a multiplier(S2). The address generation unit the counting result to an ROM and reads a prestored result at an address of the ROM matched with the counting result(S3). The address generator the read result to the multiplier(S4). The multiplier multiplies the two values received in the steps S2 and S4 by each other, and sends the multiplication result to a rounding unit(S5). The rounding unit performs a shift-right operation by as many as a result from subtraction of one bit from bits extended in the ROM and checks over whether or not the least significant bit is 0(S6). If so, the rounding unit performs additionally a shift right operation by one bit(S7) and otherwise, adds one to the result of the shift right operation and outputs it as a mean value(S8).
摘要翻译：提供一种用于在除法运算器中输出平均值的装置和方法，以最小化操作中的量化误差，以执行具有最小量化误差的简单移位操作，以通过识别是否最小化来确定舍入有效位为“0”，从而达到较高的运行速度。用于在分割算子中输出平均值的方法包括以下几个步骤。计数器计数数据输入的次数，并将计数结果发送到地址生成单元（S1）。加法器在每次输入数据时对输入的数据执行加法运算，并将加法运算的结果发送给乘法器（S2）。地址生成单元将计数结果存储到ROM中，并且在与计数结果匹配的ROM的地址上读取预存的结果（S3）。地址生成器将读取结果发送给乘法器（S4）。乘法器将步骤S2和S4中接收的两个值彼此相乘，并将相乘结果发送到舍入单元（S5）。四舍五入单元通过从ROM中扩展的比特中减去一个比特来执行移位右侧操作，并检查最低有效位是否为0（S6）。如果是这样，舍入单元另外执行一个移位右操作一位（S7），否则，将其移动到右移操作的结果中，并作为平均值输出（S8）。

69. 发明公开

KR1020080050226A 모듈러 곱셈 장치 및 설계 방법 无效
标题翻译：用于设计模块化多路复用器件的模块化多路复用器件和方法
公开(公告)号：KR1020080050226A
公开(公告)日：2008-06-05
申请号：KR1020070061565
申请日：2007-06-22
申请人： 한국전자통신연구원
发明人： 김영세 , 박영수 , 전성익
IPC分类号： G06F7/44 , G06F7/00
CPC分类号： G06F7/722 , G06F7/507 , G06F7/728
摘要： A modular multiplication device and a method for designing the same are provided to analyze and change a structure easily by achieving unity of the structure by controlling a hardware resource and performance by integrating a CSA(Carry Save Adder) module and related modules, and adding and subtracting a CSA module, thereby improving performance without designing a system in a new structure, and reducing time and cost. A modular multiplication device includes multiplexors(111,112,113) selecting an initial input value and selecting carry and sum values, a carry register(121) saving the selected carry values, a sum register(122) saving selected sum values, and at least one or more CSAs(130) executing first carry save add to a value obtained by multiplying one word bit of a current order by another word, and values outputted from the carry register and the sum register, and executing second carry save add to a result of the first carry save add and a result obtained by multiplying bit and word unit module of a current order.
摘要翻译：提供了一种模拟乘法装置及其设计方法，通过集成CSA（携带保存加法器）模块和相关模块来控制硬件资源和性能，通过实现结构的一致性，轻松分析和改变结构，并添加和减去CSA模块，从而提高性能，而不需要在新结构中设计系统，并减少时间和成本。模乘装置包括选择初始输入值并选择进位和和值的多路复用器（111,112,113），保存所选进位值的进位寄存器（121），保存所选择的和值的和寄存器（122）和至少一个或多个执行第一进位保存的CSA（130）将通过将当前顺序的一个字位乘以另一个字获得的值，以及从进位寄存器和和寄存器输出的值以及执行第二进位保存添加到第一携带保存加法和通过乘以当前顺序的位和单位单位模块获得的结果。

70. 发明公开

KR1020080026673A 곱셈 누적 연산을 위한 디지털 신호처리 장치 및 방법 有权
标题翻译：用于数字信号处理中的多媒体和累加操作的装置和方法
公开(公告)号：KR1020080026673A
公开(公告)日：2008-03-26
申请号：KR1020060091313
申请日：2006-09-20
申请人： 한국전자통신연구원
发明人： 권영수 , 구본태 , 엄낙웅
IPC分类号： G06F7/44
CPC分类号： G06F9/3001
摘要： An apparatus and a method for processing digital signals for an MAC(Multiply-and-Accumulate) operation are provided to simultaneously access a plurality of operands required for parallel MAC operations to improve memory access capacity and prevent the generation of overflow in accumulative registers in MAC blocks without having an additional clock cycle. A digital signal processor for performing an MAC operation includes a first memory(127), a second memory(126) and an MAC operation execution unit. The first memory stores a plurality of first operands and the second memory stores a plurality of second operands. The MAC operation execution unit performs parallel MAC operations on the first operands and the second operands. The MAC operation execution unit includes a plurality of parallel MAC blocks(140,141) arranged in parallel and performs parallel MAC operations on the first operands output in parallel from the first memory and the second operands output in parallel from the second memory.
摘要翻译：提供用于处理用于MAC（乘法和累加）操作的数字信号的装置和方法，以同时访问并行MAC操作所需的多个操作数，以提高存储器访问容量并防止在MAC中的累积寄存器中产生溢出块没有额外的时钟周期。用于执行MAC操作的数字信号处理器包括第一存储器（127），第二存储器（126）和MAC操作执行单元。第一存储器存储多个第一操作数，并且第二存储器存储多个第二操作数。 MAC操作执行单元对第一操作数和第二操作数执行并行MAC操作。 MAC操作执行单元包括并行排列的多个并行MAC块（140,141），并且对从第一存储器并行输出的第一操作数和从第二存储器并行输出的第二操作数执行并行MAC操作。

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