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    • 62. 发明授权
    • 고온 공정이 가능한 MEMS 디바이스 제조방법
    • 在高温过程中制造MEMS传感器的方法
    • KR101408904B1
    • 2014-06-17
    • KR1020130027539
    • 2013-03-14
    • 한국과학기술원
    • 이귀로임성규김영수
    • B81C1/00B81C3/00
    • The present invention relates to a method for fabricating a MEMS device that has an excellent etching selectivity with respect to various types of inorganic materials, is better in performance and shape than existing MEMS devices because the thickness of a film can be easily adjusted depending on devices, allows the use of existing semiconductor processes, and uses an amorphous carbon film as a sacrificial layer, including a step for forming a lower structure; a step for forming the amorphous carbon film as the sacrificial layer on the lower structure; a step for forming an insulating supporting layer on the amorphous carbon film; a step for forming an etching protection film on the insulating supporting layer, performing a single photolithography process, etching the insulating supporting layer and the amorphous carbon film at a time, and forming via holes which expose the lower structure through the insulating supporting layer and the amorphous carbon film; a step for forming an upper structure that has a sensor structure on the insulating supporting layer; a step for forming one or more through-holes through the insulating supporting layer; and a step for entirely removing the amorphous carbon film through the through-holes so that the lower structure and the upper structure are arranged apart from each other. The sensor structure is formed within a temperature section of 250°C to 450°C.
    • 本发明涉及一种制造相对于各种类型的无机材料具有优异的蚀刻选择性的MEMS器件的方法,其性能和形状比现有的MEMS器件更好,因为可以根据器件容易地调节膜的厚度 允许使用现有的半导体工艺,并且使用非晶碳膜作为牺牲层,包括形成下部结构的步骤; 在下部结构上形成作为牺牲层的无定形碳膜的步骤; 在无定形碳膜上形成绝缘支撑层的步骤; 在绝缘支撑层上形成蚀刻保护膜的步骤,进行单次光刻工艺,一次蚀刻绝缘支撑层和非晶质碳膜,形成通过绝缘支撑层露出下部结构的通孔, 无定形碳膜; 用于形成在绝缘支撑层上具有传感器结构的上部结构的步骤; 通过绝缘支撑层形成一个或多个通孔的步骤; 以及通过通孔完全除去非晶碳膜的步骤,使得下部结构和上部结构彼此分离。 传感器结构形成在250℃至450℃的温度段内。
    • 65. 发明公开
    • 적외선 센서칩, 적외선 감지기, 이의 동작 방법 및 테스트 방법
    • 红外传感器芯片,红外探测器及其操作和测试方法
    • KR1020130057482A
    • 2013-05-31
    • KR1020137009494
    • 2012-03-05
    • 한국과학기술원
    • 김희연김경민김병일경기명박재홍이귀로김경태
    • G01J5/02G01J5/20H01L31/101
    • G01J5/24G01J5/026G01J5/20H01L2224/48091H01L2224/48137H01L2224/49175H01L2924/1305H01L2924/13055H01L2924/1461H01L2924/3011H01L2924/00014H01L2924/00
    • PURPOSE: An infrared sensor chip, an infrared sensor, and an operating method and testing method thereof are provided to reduce costs for manufacturing the infrared sensor and developing the same and to improve a yield for monitoring a process. CONSTITUTION: An infrared sensor chip comprises a CMOS(Complementary Metal-Oxide Semiconductor) circuit board(110) and a bolometer(120). The CMOS circuit board is composed of an active matrix(111), a low line selecting unit, and an output multiplexer unit. The bolometer is laminated on the CMOS circuit board and composed of an active cell and a reference cell. The low line selecting unit selects a cell among the cells of the bolometer for a parametric test with respect to the bolometer of a wafer or a chip state. A voltage is applied to the selected cell. The output multiplexer unit output current properties according to the application of the voltage. [Reference numerals] (111,BB) Active matrix + SA + ADC; (120,AA) Infrared sensor; (200) Sa-FPA controller(SA/ADC/SP controller); (CC) ISP/Controller; (DD) Infrared sensor in prior art; (EE) Infrared sensor in the present invention
    • 目的:提供红外线传感器芯片,红外线传感器及其操作方法和测试方法,以降低制造红外传感器并开发红外传感器的成本,并提高监控过程的产量。 构成:红外线传感器芯片包括CMOS(互补金属氧化物半导体)电路板(110)和辐射热计(120)。 CMOS电路板由有源矩阵(111),低线选择单元和输出多路复用器组成。 测辐射热计被层压在CMOS电路板上,由活性电池和参比电池组成。 低线选择单元在测辐射热计的单元格中选择相对于晶片或芯片状态的测辐射热计的参数测试的单元。 电压被施加到所选择的单元。 输出多路复用器根据电压的应用输出电流特性。 (111,BB)有源矩阵+ SA + ADC; (120,AA)红外传感器; (200)Sa-FPA控制器(SA / ADC / SP控制器); (CC)ISP /控制器; (DD)现有技术中的红外传感器; (EE)本发明的红外线传感器
    • 66. 发明公开
    • Sa-FPA를 이용한 적외선 감지기 및 이의 제조 방법
    • 具有半主动焦平面阵列的红外探测器及其制造方法
    • KR1020120100643A
    • 2012-09-12
    • KR1020110019687
    • 2011-03-04
    • 한국과학기술원
    • 김희연김경민김병일경기명박재홍이귀로김경태
    • G01J5/02G01J5/24
    • G01J5/24G01J5/026G01J5/20H01L2224/48091H01L2224/48137H01L2224/49175H01L2924/1305H01L2924/13055H01L2924/1461H01L2924/3011H01L2924/00014H01L2924/00
    • PURPOSE: An infrared sensor using a Sa-FPA(Semi-Active Focal Plane Array) and a method for manufacturing the same are provided to inspect an operation state of the sensor in advance and to enhance chip density. CONSTITUTION: An infrared sensor using a Sa-FPA comprises a switching unit(310), a wiring routing unit(320), an ROIC(Readout Integrate Circuits) connection pad unit(330), an infrared sensor(400), an address control logic unit(300), and an ROIC chip. The switching unit is formed on a circuit substrate in advance. The wiring routing unit is formed on the circuit substrate in advance and routes electrical signals by being connected to the switching unit. The ROIC connection pad unit is formed on the circuit substrate and connected to the wiring routing unit. The infrared sensor is connected to the switching unit formed in advance by using a monolithic method. The address control logic unit is formed on the circuit substrate in advance and controls the switching unit and the wiring routing unit so that the infrared sensor generates electrical signals by sensing the infrared rays. The ROIC chip is independently manufactured and comprises a sensor chip connection pad unit being connected to the ROIC connection pad, thereby reading the electrical signals generated by the infrared sensor. [Reference numerals] (300) Address control logic unit; (310) Switching unit; (320) Wiring routing unit; (330) ROIC connection pad unit; (400) Infrared sensor
    • 目的:提供使用Sa-FPA(半活性焦平面阵列)的红外线传感器及其制造方法,以预先检测传感器的动作状态,提高芯片密度。 构成:使用Sa-FPA的红外线传感器包括开关单元(310),布线路由单元(320),ROIC(读出积分电路)连接垫单元(330),红外线传感器(400),地址控制 逻辑单元(300)和ROIC芯片。 切换单元预先在电路基板上形成。 布线布线单元预先形成在电路基板上,并通过连接到开关单元来路由电信号。 ROIC连接焊盘单元形成在电路基板上并连接到布线路径单元。 红外线传感器通过使用单片方法预先形成的开关单元连接。 地址控制逻辑单元预先形成在电路基板上,并且控制开关单元和布线布线单元,使得红外传感器通过感测红外线来产生电信号。 ROIC芯片是独立制造的,并且包括连接到ROIC连接焊盘的传感器芯片连接焊盘单元,从而读取由红外传感器产生的电信号。 (附图标记)(300)地址控制逻辑单元; (310)开关单元; (320)接线路由单元; (330)ROIC连接垫单元; (400)红外线传感器
    • 67. 发明授权
    • 저잡음 증폭기 및 무선수신기
    • 低噪声放大器和无线接收器
    • KR101123211B1
    • 2012-03-20
    • KR1020110006022
    • 2011-01-20
    • 한국과학기술원
    • 이귀로김범겸임동구최재영
    • H03F1/26H04B1/16
    • H03F1/26H03F1/223H03F1/3205H03F1/565H03F2200/372H03F2200/391H03F2200/541H04B1/16
    • PURPOSE: A low noise amplifier and a radio receiver are provided to greatly improve linearity by using the body biasing and complementary superposition of a transistor. CONSTITUTION: A low noise amplifier is composed of a complementary common source low noise amplifier(100) linearized. The linearized complementary common source low noise amplifier comprises a first primary transistor part(110), a first subsidiary transistor part(120), and a capacitor(130) for simultaneously matching optimal noise and input impedance. The first primary transistor part comprises a first NMOS(N-Channel Metal Oxide Semiconductor) transistor, a first PMOS(P-Channel Metal Oxide Semiconductor) transistor, and resistance. The first subsidiary transistor part includes a first NMOS transistor of the first primary transistor part and transistors parallely connected to the first PMOS transistor. The capacitor for simultaneous matching is communally connected to output terminals of the first primary transistor part and the first subsidiary transistor part.
    • 目的:提供低噪声放大器和无线电接收器,通过使用晶体管的体偏置和互补叠加来大大提高线性度。 构成:低噪声放大器由互补的共源低噪声放大器(100)线性化组成。 线性化互补公共源低噪声放大器包括用于同时匹配最佳噪声和输入阻抗的第一初级晶体管部分(110),第一辅助晶体管部分(120)和电容器(130)。 第一主晶体管部分包括第一NMOS(N沟道金属氧化物半导体)晶体管,第一PMOS(P沟道金属氧化物半导体)晶体管和电阻。 第一辅助晶体管部分包括第一初级晶体管部分的第一NMOS晶体管和并联连接到第一PMOS晶体管的晶体管。 用于同时匹配的电容器共同连接到第一初级晶体管部分和第一辅助晶体管部分的输出端子。
    • 68. 发明公开
    • CML 타입 D 플립-플롭 및 이를 이용한 주파수 홀수 분주기
    • CML类型D FLIP-FLOP和频率DIVIDE-BY-ODD号码
    • KR1020100027635A
    • 2010-03-11
    • KR1020080086629
    • 2008-09-03
    • 한국과학기술원
    • 이귀로신형철
    • H03K23/00H03K23/44
    • H03K23/544H03K3/35613H03K21/10
    • PURPOSE: A CML type D flip-flop and a frequency odd divider using the same are provided to easily expand a structure by adding the D flip-flops. CONSTITUTION: A first NMOS transistor(NM1) is connected between a first node(N1) and a second node(N2). A second NMOS transistor(NM2) is connected between a third node(N3) and a fourth node(N4). A third NMOS transistor(NM3) is connected between a fifth node(N5) and the second node. A fourth NMOS transistor(NM4) is connected between the fifth node and the fourth node. A fifth NMOS transistor(NM5) is connected between the third node and the fifth node. A sixth NMOS transistor is connected between the first node and the fifth node.
    • 目的:提供CML D型触发器和使用其的频率奇数分频器,以通过添加D触发器来容易地扩展结构。 构成:第一NMOS晶体管(NM1)连接在第一节点(N1)和第二节点(N2)之间。 第二NMOS晶体管(NM2)连接在第三节点(N3)和第四节点(N4)之间。 第三NMOS晶体管(NM3)连接在第五节点(N5)和第二节点之间。 第四NMOS晶体管(NM4)连接在第五节点和第四节点之间。 第五NMOS晶体管(NM5)连接在第三节点和第五节点之间。 第六NMOS晶体管连接在第一节点和第五节点之间。
    • 69. 发明公开
    • 씨모스 롬을 이용한 회로장치
    • 使用CMOS ROM的电路和设备
    • KR1020070059451A
    • 2007-06-12
    • KR1020050118296
    • 2005-12-06
    • 한국과학기술원
    • 남일구차혁규서보익김진봉이귀로
    • G11C17/10
    • G11C17/12G11C5/14G11C7/1078G11C17/18
    • A circuit apparatus is provided to implement a SOC(System On Chip) through only standard CMOS process by using a CMOS ROM instead of a conventional ROM. A circuit apparatus using a CMOS ROM can be integrated with other devices of the circuit apparatus including a ROM(Read Only Memory) implemented by a standard CMOS(Complementary Metal Oxide Semiconductor) process, through the standard CMOS process. In the ROM, first to third input stages are comprised and data is stored by a voltage applied to the input stages. A cell access transistor includes a gate and a drain forming the second input stage and a source forming the third input stage, and is enabled by a voltage applied between the gate and the source. A high voltage blocking transistor includes a gate, a drain and a source connected to the drain of the cell access transistor, and conducts a current to the source from the drain by a bias voltage applied to the gate, and prevents a high voltage applied to the third input stage from being directly applied to the cell access transistor. An anti-fuse transistor includes a gate forming the third input stage and a source and a drain connected to the drain of the high voltage blocking transistor, and a high voltage is applied to the third input stage, and a gate oxide is broken down when the cell access transistor is enabled.
    • 提供了一种电路装置,通过使用CMOS ROM代替常规ROM,仅通过标准CMOS工艺来实现SOC(片上系统)。 使用CMOS ROM的电路装置可以与包括通过标准CMOS工艺的标准CMOS(互补金属氧化物半导体)工艺实现的ROM(只读存储器)的电路装置的其它器件集成。 在ROM中,包括第一至第三输入级,并且通过施加到输入级的电压来存储数据。 电池存取晶体管包括形成第二输入级的栅极和漏极和形成第三输入级的源,并且通过施加在栅极和源极之间的电压使能。 高电压阻断晶体管包括栅极,漏极和连接到电池存取晶体管的漏极的源极,并且通过施加到栅极的偏置电压从漏极导通电流,并且防止施加到栅极 第三输入级被直接应用于单元存取晶体管。 反熔丝晶体管包括形成第三输入级的栅极和连接到高压阻断晶体管的漏极的源极和漏极,并且高电压被施加到第三输入级,并且栅极氧化物被分解为当 单元存取晶体管被使能。
    • 70. 发明授权
    • 깊은 엔 웰 씨모스 공정으로 구현된 수직형 바이폴라 정션트랜지스터를 사용한 직접 변환 수신기
    • 깊은엔웰씨모공으된된형형
    • KR100446004B1
    • 2004-08-25
    • KR1020020040821
    • 2002-07-12
    • 한국과학기술원
    • 이귀로남일구
    • H04B1/26
    • H04B1/30H03D7/1433H03D7/1441H03D7/1458H03D7/1466H03D7/1483H03D2200/0047
    • This invention is about the direct conversion receiver. It is excellent the receiving sensitivity that DC off-set, matching characteristics of the relationship of I/Q circuits and noise characteristics are improved. In order to achieve this purpose, the direct conversion receiver uses vertical bipolar junction transistor available in standard triple-well CMOS technology in the switching element of mixer and base-band analog circuits. Furthermore, as using the passive mixer in the other practical example of this invention, this invention controls the occurrence of l/f noise. As using the vertical bipolar junction transistor available in standard triple-well CMOS in the base-band analog circuits, this invention realizes the direct conversion receiver that DC off-set, matching characteristics of the relationship of I/Q circuit and noise characteristics are improved.
    • 本发明涉及直接转换接收机。 直流偏置,I / Q电路关系的匹配特性和噪声特性得到改善的接收灵敏度非常好。 为了实现这一目的,直接转换接收器在混频器和基带模拟电路的开关元件中使用标准三阱CMOS技术中可用的垂直双极结型晶体管。 而且,在本发明的另一个实际例子中使用无源混频器时,本发明控制了I / f噪声的发生。 由于在基带模拟电路中使用标准三阱CMOS中可用的垂直双极结型晶体管,本发明实现了直流偏移,I / Q电路与噪声特性关系匹配特性得到改善的直接转换接收器 。