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61. 发明公开

KR1019950009361A 금속 패턴 형성 방법 无效
公开(公告)号：KR1019950009361A
公开(公告)日：1995-04-21
申请号：KR1019930020197
申请日：1993-09-28
申请人： 에스케이하이닉스 주식회사
发明人： 전종포 , 강영수 , 정종호 , 윤중은
IPC分类号： G03F7/00

62. 发明授权

KR102005791B1 반도체 장치 有权
公开(公告)号：KR102005791B1
公开(公告)日：2019-10-01
申请号：KR1020130055481
申请日：2013-05-16
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C7/22 , G11C7/10 , G11C8/00

63. 发明授权

KR101998750B1 반도체 장치 有权
公开(公告)号：KR101998750B1
公开(公告)日：2019-10-01
申请号：KR1020120077187
申请日：2012-07-16
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C7/22 , G11C8/00

64. 发明授权

KR101989393B1 반도체 장치의 도메인 크로싱 회로 有权
公开(公告)号：KR101989393B1
公开(公告)日：2019-06-14
申请号：KR1020120093240
申请日：2012-08-24
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C8/00 , G11C8/18 , G11C7/22

65. 发明公开

KR1020140090300A 레이턴시 제어회로 및 이를 포함하는 반도체 메모리 장치 审中-实审
标题翻译：延迟控制电路和包括其的半导体存储器件
公开(公告)号：KR1020140090300A
公开(公告)日：2014-07-17
申请号：KR1020120149966
申请日：2012-12-20
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C8/18 , G11C7/22
CPC分类号： G11C7/222 , G11C7/225 , G11C2207/2254 , G11C2207/2272 , H03K5/1565
摘要： The present invention relates to a latency control circuit and a semiconductor memory device including the same, including an internal command generating unit for generating an internal command in response to an external command; a clock delay unit for delaying an external clock by an operation delay amount of the internal command generating unit and generating an internal clock; a command synchronization unit for synchronizing the internal command sequentially with the internal clock and the external clock for compensating the operation delay amount of the internal commend generating unit and generating a synchronization command; and a latency shifting unit for shifting the synchronization command by the number of set latency on the basis of the external clock.
摘要翻译：等离子体控制电路及其半导体存储装置技术领域本发明涉及等离子体控制电路及包括该延迟控制电路的半导体存储装置，其包括内部指令生成部，其根据外部命令生成内部命令; 时钟延迟单元，用于通过内部命令产生单元的操作延迟量来延迟外部时钟并产生内部时钟; 命令同步单元，用于与内部时钟和外部时钟顺序地同步内部命令，用于补偿内部表征生成单元的操作延迟量并产生同步命令; 以及延迟移位单元，用于基于外部时钟将同步命令移位设定的等待时间。

66. 发明公开

KR1020140069650A 집적회로 및 집적회로의 동작방법 审中-实审
标题翻译：集成电路及其操作方法
公开(公告)号：KR1020140069650A
公开(公告)日：2014-06-10
申请号：KR1020120137186
申请日：2012-11-29
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C7/10
CPC分类号： H03K19/0005
摘要： The present invention relates to an integrated circuit with a multiple die package structure including a plurality of semiconductor devices which include on die termination (ODT) circuits. In the integrated circuit with the multiple die package structure including the semiconductor devices, each semiconductor device includes an active termination circuit which is controlled to off in the disable state of an active termination setting code, a multiple die package information signal generating unit, and a forced termination unit which forcedly switches the active termination setting code into the disable state in response to the multiple die package information signal.
摘要翻译：本发明涉及一种具有多管芯封装结构的集成电路，该多晶片封装结构包括多个半导体器件，其包括在管芯端接（ODT）电路上。在具有包括半导体器件的多管芯封装结构的集成电路中，每个半导体器件包括在有源端接设置代码的禁止状态下被控制为截止的有源终端电路，多管芯封装信息信号生成单元和强制终端单元，其响应于多个管芯封装信息信号强制将有效端接设置代码切换到禁止状态。

67. 发明公开

KR1020140000999A 온 다이 터미네이션 회로 审中-实审
标题翻译：连接终止电路
公开(公告)号：KR1020140000999A
公开(公告)日：2014-01-06
申请号：KR1020120069155
申请日：2012-06-27
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： H03K19/0005
摘要： Provided is an on-die termination circuit to enable stable on-die termination function control and the on-die termination circuit comprises: a clock signal generation block configured to output a clock signal in response to a clock enable signal; a termination block configured to perform a termination operation on an input/output pad in response to the clock signal, a first termination control signal, and a second termination control signal; a first termination control block configured to generate the first termination control signal by controlling a latency of a first command in response to the clock signal and a latency control signal; a second termination control block configured to control a latency of a second command and to generate the second termination control signal in response to the clock signal and the latency control signal; and a clock enable signal generation block configured to generate the clock enable signal in response to the first command, the first termination control signal, and the second command. [Reference numerals] (110) Delay locked loop (DLL); (120) Termination block
摘要翻译：提供了一种片上终端电路，用于实现稳定的片上终端功能控制，并且片上终端电路包括：时钟信号产生模块，被配置为响应于时钟使能信号输出时钟信号; 终端块，被配置为响应于所述时钟信号，第一终止控制信号和第二终止控制信号在输入/输出焊盘上执行终止操作; 第一终止控制块，被配置为通过响应于所述时钟信号和等待时间控制信号控制第一命令的等待时间来生成所述第一终止控制信号; 第二终止控制块，被配置为响应于所述时钟信号和等待时间控制信号来控制第二命令的等待时间并产生所述第二终止控制信号; 以及时钟使能信号生成块，被配置为响应于所述第一命令，所述第一终止控制信号和所述第二命令而产生所述时钟使能信号。（110）延迟锁定环（DLL）; （120）终止块

68. 发明授权

KR101062777B1 반도체 메모리 장치 有权
公开(公告)号：KR101062777B1
公开(公告)日：2011-09-06
申请号：KR1020100040547
申请日：2010-04-30
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C7/10 , G11C29/00
CPC分类号： G11C29/025 , G11C29/028 , G11C29/1201 , G11C29/48 , G11C29/50008
摘要： 본 발명은 반도체 메모리 장치에 관한 것으로, 라인 조절 신호의 레벨에 응답하여 터미네이션 저항값을 조정하는 코드 신호 및 반도체 메모리 장치 칩 내의 테스트를 위한 테스트 모드 신호 중 어느 하나의 신호를 선택적으로 공용 글로벌 라인으로 출력하는 라인 조절부를 포함한다.

69. 发明公开

KR1020100006887A 캘리브래이션 회로, 온 다이 터미네이션 장치 및 반도체 메모리 장치 有权
标题翻译：分离电路，终端设备和半导体存储器件
公开(公告)号：KR1020100006887A
公开(公告)日：2010-01-22
申请号：KR1020080067200
申请日：2008-07-10
申请人： 에스케이하이닉스 주식회사 , 한양대학교 산학협력단
发明人： 정종호 , 이재진 , 곽계달 , 박경수 , 최재웅 , 채명준
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C7/1048 , G11C5/14 , G11C7/22 , G11C2207/2254 , H03K19/0005
摘要： PURPOSE: A calibration circuit, on die termination device, and semiconductor memory device are provided to eliminate accurately the impedance mismatch. CONSTITUTION: The comparator(609, 611) compares the voltage of the full down calibration node with the reference voltage of the reference voltage generator(607). The pull-up control voltage and pull-down control voltage are generated. The full down calibration resistance circuit(605) comprises the pull-down control voltage. The dummy calibration resistance circuit(603) and full down calibration resister circuit generates the pull-down control voltage based on 'the pull-up control voltage which becomes with the pull-up calibration resister circuit'.
摘要翻译：目的：提供校准电路，芯片终端器件和半导体存储器件，以准确消除阻抗失配。构成：比较器（609,611）将全下降校准节点的电压与参考电压发生器（607）的参考电压进行比较。产生上拉控制电压和下拉控制电压。全向下校准电阻电路（605）包括下拉控制电压。虚拟校准电阻电路（603）和全向下校准电路电路基于“上拉校准电阻电路成为的上拉控制电压”产生下拉控制电压。

70. 发明公开

KR1020090069668A 온도에 따라 슬루율을 조절하는 반도체장치 无效
标题翻译：控制其全部速率的半导体器件
公开(公告)号：KR1020090069668A
公开(公告)日：2009-07-01
申请号：KR1020070137400
申请日：2007-12-26
申请人： 에스케이하이닉스 주식회사
发明人： 정종호
IPC分类号： G11C11/406 , G11C11/4096
CPC分类号： G11C11/40626 , G11C7/04 , G11C7/1051 , G11C11/4096 , G11C2207/2254
摘要： A semiconductor device is provided to stably output a data by increasing a slew rate of an output driver according to an increase of temperature. A semiconductor device includes a temperature information output part(310), a pre-driver(320), and a main driver(330). The temperature information output part outputs temperature information(TEMPA,TEMPB,TEMPC) inside the semiconductor device. The pre-driver generates one or more driving signals(UP-PRE,DN-PRE) according to a logic level of an output data. An initial slew rate of the driving signal is determined by a test mode signal. The pre-driver changes the slew rate of the driving signal according to the temperature information inside the semiconductor device. The main driver outputs data in response to the driving signal. A slew rate of the output data of the main driver is changed according to a change of a slew rate of the driving signal.
摘要翻译：提供一种半导体器件，用于通过根据温度的升高增加输出驱动器的转换速率来稳定地输出数据。半导体器件包括温度信息输出部分（310），预驱动器（320）和主驱动器（330）。温度信息输出部输出半导体器件内的温度信息（TEMPA，TEMPB，TEMPC）。预驱动器根据输出数据的逻辑电平产生一个或多个驱动信号（UP-PRE，DN-PRE）。驱动信号的初始转换速率由测试模式信号确定。预驱动器根据半导体器件内的温度信息来改变驱动信号的转换速率。主驱动器响应于驱动信号输出数据。主驱动器的输出数据的转换速率根据驱动信号的转换速率的变化而改变。

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