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51. 发明公开

KR20100035327A Solid state drive including synchronization system & stabilization method for data of nonvolatile memory 审中-公开
标题翻译：固态驱动器，包括非易失性存储器数据的同步系统和稳定方法
公开(公告)号：KR20100035327A
公开(公告)日：2010-04-05
申请号：KR20080094640
申请日：2008-09-26
申请人： MTRONSTORAGE TECHNOLOGY CO LTD
发明人： JEON HYUNG GWAN , YANG YOUNG SOUK , YANG CHAN YOUNG
IPC分类号： G06F13/16 , G06F12/00 , G11C16/00
摘要： PURPOSE: A solid state drive with a synchronization device and a method for stabilizing data of a nonvolatile memory are provided to simultaneously stop the operation of a flash controller and a nonvolatile memory. CONSTITUTION: An SSD(200) includes a logic unit(210) and a memory bus slot(220). The logic unit includes a flash controller, a central processing unit and a volatile memory. In the memory bus slot, a nonvolatile memory(230) is connected. If input power is interrupted, a voltage detector(310) connected to an input power unit of the SSD generates an operating signal. The first reset unit(320) generates a digital signal. The second reset unit(330) is connected to a reset pin(211) within the flash controller.
摘要翻译：目的：提供具有同步装置的固态驱动器和用于稳定非易失性存储器的数据的方法，以同时停止闪存控制器和非易失性存储器的操作。构成：SSD（200）包括逻辑单元（210）和存储器总线槽（220）。逻辑单元包括闪存控制器，中央处理单元和易失性存储器。在存储器总线插槽中，连接有非易失性存储器（230）。如果输入功率中断，连接到SSD的输入功率单元的电压检测器（310）产生操作信号。第一复位单元（320）产生数字信号。第二复位单元（330）连接到闪存控制器内的复位引脚（211）。

52. 发明公开

KR20100034878A Non-volatile memory device 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：KR20100034878A
公开(公告)日：2010-04-02
申请号：KR20080094090
申请日：2008-09-25
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： SEL JONG SUN , CHOI JUNG DAL , LIM NAM SU , OH IN WOOK
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C5/025 , G11C16/08
摘要： PURPOSE: A non-volatile memory device is provided to reduce the number of pass transistors connected to each word line by sharing a word line between adjacent blocks. CONSTITUTION: A first and a second memory regions have a plurality of strings, respectively. Each string comprises a string selection transistor, a ground selection transistor, and a memory cells. A string selection transistor(SST) is connected to the string selection line. The ground selection transistor(GST) is connected to the ground selection line. A memory cell(M0~M31) is respectively connected to corresponding word lines. Word lines and a ground selection line forms a closed circuit.
摘要翻译：目的：提供一种非易失性存储器件，以通过在相邻块之间共享字线来减少连接到每个字线的通过晶体管的数量。构成：第一和第二存储区分别具有多个串。每个串包括串选择晶体管，接地选择晶体管和存储单元。字符串选择晶体管（SST）连接到字符串选择线。接地选择晶体管（GST）连接到地选线。存储单元（M0〜M31）分别与对应的字线连接。字线和地线选择线形成闭路。

53. 发明公开

KR1020100024800A 비휘발성 메모리 소자 및 그 동작 방법 无效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：KR1020100024800A
公开(公告)日：2010-03-08
申请号：KR1020080083518
申请日：2008-08-26
申请人： 삼성전자주식회사
发明人： 이명재 , 유인경 , 박영수
IPC分类号： H01L27/115 , G11C16/00
CPC分类号： G11C7/18 , G11C5/02 , G11C5/025 , G11C8/14 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C17/16 , G11C2213/71 , H01L27/2436
摘要： PURPOSE: A non-volatile memory device and a method for operating the same are provided to produce a highly integrated non-volatile memory device by increasing the number of stacked memory cells. CONSTITUTION: A plurality of variable resistors(R) is arranged on one or more layers. The variable resistors have a data storage capacity. A common bit plane(CPn, CPn+1) is combined with the first step of a corresponding variable resistor. The common bit plane is laminated with one or more layers. A plurality of bit lines(BL1, BL2) is combined with the second step of the variable resistances. A plurality of cell selection transistors(Tsc) is combined between the bit lines and the variable resistances. A plurality of word lines(WL1, WL2) controls the on-off state of the cell selection transistors.
摘要翻译：目的：提供非易失性存储器件及其操作方法，以通过增加堆叠的存储器单元的数量来产生高度集成的非易失性存储器件。构成：多个可变电阻器（R）布置在一个或多个层上。可变电阻具有数据存储容量。公共位平面（CPn，CPn + 1）与对应的可变电阻器的第一步进行组合。公共位平面层叠有一层或多层。多个位线（BL1，BL2）与可变电阻的第二步进行组合。多个单元选择晶体管（Tsc）组合在位线和可变电阻之间。多个字线（WL1，WL2）控制单元选择晶体管的导通截止状态。

54. 发明公开

KR1020100022788A 저항체를 이용한 비휘발성 메모리 장치 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：KR1020100022788A
公开(公告)日：2010-03-03
申请号：KR1020080081466
申请日：2008-08-20
申请人： 삼성전자주식회사
发明人： 최병길
IPC分类号： G11C16/00 , G11C13/02
CPC分类号： G11C13/004 , G11C5/063 , G11C11/16 , G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： PURPOSE: A nonvolatile memory device with a variable resistive element is provided to improve performance in case of a reading operation by setting longer discharging time for writing global bit-lines than the quenching time of current which flows through the nonvolatile memory cell of memory banks. CONSTITUTION: Memory banks(110_1 to 110_8) include a plurality of nonvolatile memory cells. The plurality of nonvolatile memory cells has different resistance levels based on data to be saved. Writing global bit-lines(WGBL0 to WGBLn) are arranged to be shared in the memory banks. Reading global bit-lines are arranged to be shared in the memory banks. The discharging time for the writing global bit-lines is longer than the quenching time for current which flows through the nonvolatile memory cell of the memory banks.
摘要翻译：目的：提供一种具有可变电阻元件的非易失性存储器件，以便在读取操作的情况下，通过设置比流过存储体的非易失性存储单元的电流的淬灭时间更长的写入全局位线的放电时间来提高性能。构成：存储体（110_1至110_8）包括多个非易失性存储单元。多个非易失性存储单元基于要保存的数据具有不同的电阻电平。编写全局位线（WGBL0至WGBLn）被布置为在存储体中共享。读取全局位线被布置为在存储体中共享。写入全局位线的放电时间长于流过存储体的非易失性存储单元的电流的淬灭时间。

55. 发明公开

KR1020100020265A 저항체를 이용한 비휘발성 메모리 장치 无效
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：KR1020100020265A
公开(公告)日：2010-02-22
申请号：KR1020080078970
申请日：2008-08-12
申请人： 삼성전자주식회사
发明人： 최병길 , 조백형 , 김혜진
IPC分类号： G11C16/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C2213/72
摘要： PURPOSE: A nonvolatile memory device using variable resistive element is provided to improve the read operation by including a read bias part which offers a read bias to a sensing node to read a resistance level of a nonvolatile memory cell. CONSTITUTION: Memory blocks(BLK0, BLK8) comprise a matrix of nonvolatile memory cells. A bit line(BL0) is coupled to a row of nonvolatile memory cells of each memory block. A read bias part offers a read bias to a sensing node selectively coupled to a bit line included in each memory block. The read bias part comprises first and second read bias part. The first and second read bias parts(146_0, 146_8) respectively offer the first read bias and the second read bias in different level.
摘要翻译：目的：提供使用可变电阻元件的非易失性存储器件，通过包括向读出节点提供读取偏置以读取非易失性存储器单元的电阻电平的读偏置部分来改善读操作。构成：存储器块（BLK0，BLK8）包括非易失性存储器单元的矩阵。位线（BL0）耦合到每个存储器块的非易失性存储器单元行。读偏置部分向选择性地耦合到每个存储器块中包括的位线的感测节点提供读偏置。读偏置部分包括第一和第二读偏置部分。第一和第二读偏置部分（146_0,146_8）分别提供不同级别的第一读偏置和第二读偏压。

56. 发明授权

KR100937564B1 비휘발성 반도체 기억 장치 및 그 기입 방법 失效
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：KR100937564B1
公开(公告)日：2010-01-19
申请号：KR1020077029001
申请日：2005-06-20
申请人： 후지쯔 가부시끼가이샤
发明人： 기노시따,겐따로
IPC分类号： G11C16/00 , G11C11/21
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/31 , G11C2213/75 , G11C2213/79
摘要： 고저항 상태와 저저항 상태를 기억하고, 전압의 인가에 의해 고저항 상태와 저저항 상태를 절환하는 저항 기억 소자를 갖는 비휘발성 반도체 기억 장치의 기입 방법에서, 저항 기억 소자에 병렬로 접속된 가변 저항 소자를 설치하고, 저항 기억 소자에 전압을 인가하여 고저항 상태와 저저항 상태를 절환할 때에, 저항 기억 소자에 전압을 인가하는 기입 회로와 저항 기억 소자 및 가변 저항 소자의 합성 저항이 임피던스 정합하도록, 저항 기억 소자의 저항 상태에 따라서 가변 저항 소자의 저항값을 설정한다.
메모리 셀, 저항 기억 소자, 가변 저항 소자, 기입 회로, 셀 선택 트랜지스터, 합성 저항, 임피던스

57. 发明授权

KR100935949B1 반도체 장치 및 그의 제어 방법 失效
标题翻译：半导体器件及其控制方法
公开(公告)号：KR100935949B1
公开(公告)日：2010-01-12
申请号：KR1020077030629
申请日：2005-06-28
申请人： 스펜션 엘엘씨 , 스펜션 저팬 리미티드
发明人： 오가와아키라 , 야노마사루
IPC分类号： G11C16/00
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： 본 발명은, 비휘발성 메모리 셀 어레이(10) 내에 형성된 코어 셀(12)에 접속된 제1 전류 전압 변환 회로(16)와, 레퍼런스 셀(22)에 레퍼런스 셀 데이터 라인(24)을 통하여 접속된 제2 전류 전압 변환 회로(26)와, 제1 전류 전압 변환 회로의 출력과 제2 전류 전압 변환 회로의 출력을 센싱하는 센스 증폭기(18)와, 레퍼런스 셀 데이터 라인의 전압값과 소정의 전압값을 비교하는 비교 회로(28)와, 레퍼런스 셀 데이터 라인의 프리차지시에 레퍼런스 셀 데이터 라인의 전압값이 소정의 전압값보다 낮으면 레퍼런스 셀 데이터 라인을 차지하는 차지 회로(30)를 구비한 반도체 장치 및 그의 제어 방법이다. 본 발명에 의하면, 레퍼런스 셀 데이터 라인의 프리차지 시간을 단축하여 데이터의 독출 시간을 단축할 수 있다.

58. 发明公开

KR1020090117760A 고체 상태 드라이브 有权
标题翻译：半导体存储器件
公开(公告)号：KR1020090117760A
公开(公告)日：2009-11-12
申请号：KR1020097018036
申请日：2008-09-22
申请人： 가부시끼가이샤 도시바
发明人： 스기따,마사또 , 마에다,게이지
IPC分类号： G11C16/00 , G11C16/30 , G11C16/06
CPC分类号： G11C16/30
摘要： A plurality of flash memories 2, a connector for establishing connection with a host apparatus 100, a cache memory 4 for data transmission between the flash memories 2 and the host apparatus 100, a drive control circuit 3 that controls the data transmission between the flash memories 2 and the host apparatus 100, and a power supply circuit 5 that converts an external power supply voltage into an internal power supply voltage are mounted on a substrate. A fuse 10 that protects at least the flash memories 2 from an overcurrent is provided on the substrate.
摘要翻译：多个闪速存储器2，用于建立与主机设备100的连接的连接器，用于闪速存储器2和主机设备100之间的数据传输的高速缓存存储器4，控制闪存之间的数据传输的驱动控制电路3 2和主机装置100以及将外部电源电压转换为内部电源电压的电源电路5安装在基板上。在基板上设置有至少保护闪速存储器2免于过电流的保险丝10。

59. 发明公开

KR1020090117748A 메모리 시스템 有权
标题翻译：记忆系统
公开(公告)号：KR1020090117748A
公开(公告)日：2009-11-12
申请号：KR1020097017688
申请日：2009-01-22
申请人： 가부시끼가이샤 도시바
发明人： 나가도미야스시
IPC分类号： G11C16/00 , G11C16/26 , G11C16/06
CPC分类号： G11C16/32 , G11C16/0483 , G11C16/26 , G11C29/028 , G11C29/42
摘要： A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit.
摘要翻译：存储系统包括非易失性存储器，控制非易失性存储器的控制电路，控制控制电路的MPU以及根据本发明的一个方面与主机进行通信的接口电路，其中控制电路包括：读取单元，其向非易失性存储器输出读取使能信号以读取数据; 延迟单元，其延迟通过返回读取使能信号而获得的信号并将该信号作为时钟输出;以及锁存单元，其通过使用从延迟单元输出的时钟锁存并输出从非易失性存储器读取的数据。

60. 发明公开

KR1020090113623A 플래시 메모리 시스템 및 그 동작 제어방법 无效
标题翻译：控制闪存系统
公开(公告)号：KR1020090113623A
公开(公告)日：2009-11-02
申请号：KR1020080039435
申请日：2008-04-28
申请人： 엘지전자 주식회사
发明人： 김종명
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G06F13/1668 , G11C16/26
摘要： PURPOSE: A flash memory system and an operation controlling method thereof are provided to change the capacity of a flash memory system by attaching or detaching the flash memory. CONSTITUTION: A flash memory chip attaching unit(150) attaches a flash memory(100). A flash controller(200) produces the total storage capacity by adding up the storage capacity of the flash memory attached to the memory chip attaching unit. The flash controller transmits the flash memory ID read command to the memory chip attaching unit. The flash controller determines whether the flash memory is attached or not according to the signal transmitted from a memory chip attaching unit corresponding to the transmitted ID read command. The flash controller successively transmits the ID read command to at least two memory chip attaching units.
摘要翻译：目的：提供闪存系统及其操作控制方法，以通过附加或拆卸闪存来改变闪存系统的容量。构成：闪存芯片连接单元（150）附接闪速存储器（100）。闪存控制器（200）通过将连接到存储器芯片附接单元的闪存的存储容量相加来产生总存储容量。闪存控制器将闪存ID读取命令发送到存储器芯片附接单元。闪存控制器根据与发送的ID读取命令对应的从存储器芯片附接单元发送的信号来确定闪存是否被附加。闪存控制器将ID读取命令连续地发送到至少两个存储器芯片附接单元。

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