专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

KR100892296B1 반도체 테스트 패턴신호의 체배 장치 有权
标题翻译：用于半导体测试信号的多用途设备
公开(公告)号：KR100892296B1
公开(公告)日：2009-04-08
申请号：KR1020070107080
申请日：2007-10-24
申请人： 주식회사 아이티엔티 , 에스케이하이닉스 주식회사
发明人： 장경훈 , 오세경
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G01R31/31928 , G11C29/56004 , G11C29/56012
摘要： A multiply apparatus for a semiconductor test pattern signal is provided to reduce multiplying time of a pattern signal by alternatively and simultaneously outputting pattern signals by a plurality of pattern signal generating units. The first pattern signal generating unit(110) generates and outputs the first semiconductor test pattern signal. The second pattern signal generating unit(120) generates and outputs the second semiconductor test pattern signal. An encoder unit(130) converts and outputs signals inputted to the first pattern signal generating unit and the second pattern signal generating unit into different pattern systems. The first formatter(140) combines and outputs a timing value with a signal inputted from the encoder unit. The second formatter(150) combines a different timing value from the first formatter with a signal inputted from the encoder unit. A frequency multiplying unit(160) multiplies the signals inputted from the first and second formatters and outputs the signal by one signal.
摘要翻译：提供了用于半导体测试图案信号的乘法装置，以通过交替地减少图案信号的乘法时间，并且通过多个图案信号生成单元同时输出图案信号。第一图案信号生成单元（110）生成并输出第一半导体测试图案信号。第二图案信号生成单元（120）生成并输出第二半导体测试图案信号。编码器单元（130）将输入到第一图案信号生成单元和第二图案信号生成单元的信号转换并输出到不同的图案系统中。第一格式器（140）组合并输出与编码器单元输入的信号的定时值。第二格式器（150）将来自第一格式化器的不同定时值与从编码器单元输入的信号组合。倍频单元（160）将从第一和第二格式化器输入的信号相乘并将信号输出一个信号。

52. 发明授权

KR100860826B1 좁은 출력 펄스를 갖는 자동 테스트 장치 有权
标题翻译：具有NARROW输出脉冲的自动测试设备
公开(公告)号：KR100860826B1
公开(公告)日：2008-09-30
申请号：KR1020037001189
申请日：2001-07-17
申请人： 테라다인 인코퍼레이티드
发明人： 사르체프로날드에이.
IPC分类号： G01R31/319
CPC分类号： G01R31/31928 , G01R31/31922
摘要： Automatic test equipment suitable for testing high speed semiconductor devices. The test equipment includes a formatter circuit with a flip flop that produces an output in the desired format even if the edge signals that control the setting and resetting of the flip flop overlap. The flip flop allows the test system to generate outputs with narrow pulses, and can generate output pulses that are narrower than the controlling edge signals.

53. 发明公开

KR1020060019575A 시험 장치 无效
标题翻译：测试设备
公开(公告)号：KR1020060019575A
公开(公告)日：2006-03-03
申请号：KR1020057023474
申请日：2004-06-04
申请人： 주식회사 아도반테스토
发明人： 치바노리아키 , 츠루키야스타카
IPC分类号： G01R31/3183 , G01R31/26 , H01L21/66
CPC分类号： G01R31/31922 , G01R31/31928
摘要： A testing device comprises a first reference clock producing section for producing a first reference clock, a first test rate producing section for producing a first test rate clock on the bass of the first reference clock, a first driver for supplying a first test pattern to an electronic device on the basis of the first rate clock, a second reference clock producing section for producing a second reference clock, a first phase-locking section for phase-locking the second reference clock at the first test rate clock, a second test rate producing section for producing a second test rate clock on the basis of the phase-locked second reference clock, and a second driver for supplying a second test pattern to an electronic device on the basis of the second test rate clock.
摘要翻译：测试装置包括用于产生第一参考时钟的第一参考时钟产生部分，用于产生第一参考时钟的低音上的第一测试速率时钟的第一测试速率产生部分，用于向第一参考时钟提供第一测试模式的第一驱动器，基于第一速率时钟的电子设备，用于产生第二参考时钟的第二参考时钟产生部分，用于以第一测试速率时钟相位锁定第二参考时钟的第一相位锁定部分，产生第二测试速率的第二测试速率基于所述锁相第二参考时钟产生第二测试速率时钟的部分，以及用于基于所述第二测试速率时钟向第二测试模式提供第二测试模式的第二驱动器。

54. 发明公开

KR1020060009951A 시험 장치 및 테스트 모듈 无效
标题翻译：测试装置和测试模块
公开(公告)号：KR1020060009951A
公开(公告)日：2006-02-01
申请号：KR1020057022203
申请日：2004-05-21
申请人： 주식회사 아도반테스토
发明人： 와시즈노부에이
IPC分类号： G01R31/317
CPC分类号： G01R31/31926 , G01R31/31919 , G01R31/31928
摘要： There is provided a test apparatus for testing an electronic device having a plurality of device terminals for receiving a signal. The test apparatus includes: an operation condition output section for outputting an operation condition indicating the operation of a signal to be given to a device terminal while correlating the operation condition to the device terminal; and a test module for giving a test signal to be used for testing an electronic device to the electronic device according to the operation indicated by the operation condition. The test module has: a plurality of apparatus terminals each electrically connected to one of the device terminals so as to give a test signal to the device terminal; a terminal correspondence storage section for storing terminal correspondence information indicating the correspondence between each device terminal and an apparatus terminal connected to the device terminal; and an operation condition setting section for selecting an apparatus terminal to be connected to the device terminal correlated to the operation condition, according to the terminal correspondence information and setting an operation condition in the apparatus terminal selected.
摘要翻译：提供了一种用于测试具有用于接收信号的多个设备终端的电子设备的测试设备。所述测试装置包括：操作条件输出部分，用于在将所述操作条件与所述设备终端相关联时，输出指示要向所述设备终端发送的信号的操作的操作条件; 以及测试模块，用于根据操作条件指示的操作向电子设备提供用于测试电子设备的测试信号。测试模块具有：多个设备端子，每个设备端子电连接到设备端子之一，以便向设备端子提供测试信号; 终端对应存储部分，用于存储表示每个设备终端与连接到设备终端的设备终端之间的对应关系的终端对应信息; 以及操作条件设定部分，用于根据终端对应信息选择要连接到与操作条件相关的设备终端的设备终端，并且在所选择的设备终端中设置操作条件。

55. 发明公开

KR1020050121716A 집적회로들에서의 타이밍 관련 불량들을 디버깅하기 위한이벤트 기반 테스트 방법 无效
标题翻译：基于事件的测试方法，用于调试整合电路中的时序相关故障
公开(公告)号：KR1020050121716A
公开(公告)日：2005-12-27
申请号：KR1020057019219
申请日：2004-04-07
申请人： 가부시키가이샤 어드밴티스트
发明人： 프라마닉,안칸 , 사웨,시다하스 , 래쥬맨,로치트
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31919 , G01R31/31937
摘要： A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference signal related to the failure, identifying a portion of the reference signal, and incrementally changing a timing of events in the portion of the reference signal to detect change in the reponse output from the DUT.
摘要翻译：使用基于事件的半导体测试系统来调试IC设备的故障的测试方法能够区分与时序相关的故障与其他故障。测试方法包括以下步骤：将测试信号施加到DUT并评估DUT的响应输出，检测响应输出中的故障，识别与故障相关的参考信号，识别参考信号的一部分，以及逐渐改变参考信号部分的事件定时，以检测来自DUT的响应输出的变化。

56. 发明公开

KR1020050074473A 시험장치 및 시험방법 失效
标题翻译：测试设备和测试方法
公开(公告)号：KR1020050074473A
公开(公告)日：2005-07-18
申请号：KR1020057005786
申请日：2003-09-30
申请人： 주식회사 아도반테스토
发明人： 타나카코우이치 , 도이마사루 , 사토신야
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31922
摘要： a timing generation section for successively generating a plurality of timing signals indicating different timings during a test of a setup test or a hold test according to a first offset value given before start of the setup test or the hold test; a pattern generation section for generating a clock signal and a data signal; a waveform shaping section for successively shifting a data signal phase for a clock signal according to the timing signal successively generated and successively supplying the clock signal and the phase-shifted data signal to the device to be tested; and a judgment section for calculating the setup time or hold time of the device to be tested according to the storage data containing the data signal stored by the device to be tested.
摘要翻译：定时产生部分，用于在建立测试或保持测试的测试期间根据在建立测试或保持测试开始之前给出的第一偏移值连续生成指示不同定时的多个定时信号; 用于产生时钟信号和数据信号的模式产生部分; 波形整形部分，用于根据连续生成的定时信号连续地移位数据信号相位，并将时钟信号和相移数据信号依次提供给被测器件; 以及判断部分，用于根据包含被测试装置存储的数据信号的存储数据来计算待测试装置的建立时间或保持时间。

57. 发明授权

KR100411528B1 반도체 디바이스의 시험 장치 및 시험 방법 失效
标题翻译： 반도체디바이스의시험장치및시험방법
公开(公告)号：KR100411528B1
公开(公告)日：2003-12-18
申请号：KR1020010023088
申请日：2001-04-27
申请人： 가부시키가이샤 아드반테스트
发明人： 나카야마히로야스
IPC分类号： G01R31/3183 , G01R31/26 , H01L21/66
CPC分类号： G01R31/31921 , G01R31/31919 , G01R31/31928
摘要： A test signal supplying apparatus for a semiconductor device testing apparatus that tests a plurality of semiconductor devices; including: a test pattern generating unit for outputting an input signal pattern to the semiconductor devices and receiving a match signal which indicates the semiconductor device, to which the input signal pattern is applied, is passed in the test; and a match-fail detecting unit for receiving the match signal to detect a semiconductor device that fails in the test and outputting a match-fail signal for identifying the semiconductor device that fails in the test; and a stop signal output unit connected to the match-fail detecting unit for receiving the match-fail signal from the match-fail detecting unit, storing the match-fail signal, and outputting a first stop signal that stops an application of the input signal pattern to the semiconductor devices that fail in the test identified by the stored match-fail signal.
摘要翻译：一种用于测试多个半导体器件的半导体器件测试装置的测试信号供应装置; 包括：测试模式生成单元，用于向所述半导体器件输出输入信号模式，并且接收指示应用了所述输入信号模式的所述半导体器件的匹配信号在测试中通过; 以及匹配失败检测单元，用于接收匹配信号以检测测试失败的半导体器件并输出用于识别测试失败的半导体器件的匹配失败信号; 以及停止信号输出单元，连接到匹配失败检测单元，用于接收来自匹配失败检测单元的匹配失败信号，存储匹配失败信号，并输出停止施加输入信号的第一停止信号模式到由存储的匹配失败信号识别的测试中失败的半导体器件。

58. 发明授权

KR100356725B1 반도체 시험 장치 失效
标题翻译：半导体测试设备
公开(公告)号：KR100356725B1
公开(公告)日：2002-10-19
申请号：KR1019990017282
申请日：1999-05-14
申请人： 가부시키가이샤 아드반테스트
发明人： 오치아이가츠미 , 마스다노리유키
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G01R31/31922 , G01R31/31928
摘要： 본발명은핀·멀티플렉스모드를이용하여 DUT를테스트하는퍼핀·테스터에관한것으로, 기준클록의배속도까지동작을가능하게한 반도체시험장치를실현하는것을목적으로한다. 이목적을달성하기위해, 핀·멀티플렉스모드를이용하여 DUT를테스트하는퍼핀·테스터의반도체시험장치에있어서, 유저가설정한 1테스트주기중에서복수의유저설정패턴신호를파형메모리로부터수신하여, 동일패턴엣지신호가연속할때에후속하는패턴엣지신호를소거하여, 다른패턴엣지신호의실제로변화하는패턴엣지신호만을타이밍발생기로전송하고, 타이밍발생기는실제로변화하는패턴엣지신호를차례로발생시켜서파형정형기에전송하도록한 가상타이밍발생기를파형메모리와타이밍발생기사이에설치한반도체시험장치를제공한다.
摘要翻译：本发明涉及一种用于使用管脚多路复用模式测试DUT的吸气测试器，并且目的在于实现一种能够以高达参考时钟倍速的速度工作的半导体测试装置。为了实现关注小，根据海雀的半导体测试装置，利用销，复用模式来测试DUT的测试仪，以接收多个从所述波形存储器中的用户设定图形信号的在一个测试周期中的用户设定中，相同的擦除在连续图案边缘信号之后的图案边缘信号，波形整形器仅透射图案边缘信号实际上在不同的图案边缘信号改变到定时发生器以及通过生成图案边缘信号定时发生器反过来实际改变以及用于将虚拟定时发生器发送到波形存储器和定时发生器的虚拟定时发生器。

59. 发明授权

KR100295250B1 반도체 메모리 시험장치 및 시험방법 失效
标题翻译：半导体存储器测试装置和测试方法
公开(公告)号：KR100295250B1
公开(公告)日：2001-07-12
申请号：KR1019990023791
申请日：1999-06-23
申请人： 가부시키가이샤 아드반테스트
发明人： 하시모토준
IPC分类号： G11C29/00
CPC分类号： G01R31/31928 , G01R31/31937 , G11C29/26
摘要： 판독되는데이터의파형이확정하고있는시간이매우짧은고속메모리를동시에복수개시험할수 있는반도체메모리시험장치및 방법을제공한다. 시험개시전에복수개의피시험메모리로부터각각출력되는클록의위상을측정하는위상측정장치와, 이위상측정장치에의하여측정된위상에대응하는지연시간이각각설정되는복수의가변지연회로를설치하고, 타이밍발생기로부터복수의논리비교기에공급된비교타이밍신호를이들가변지연회로를통하여상기논리비교기에각각부여한다. 이로서이들논리비교기에부여되는비교타이밍신호는대응하는가변지연회로에설정된지연시간만큼각각지연되므로, 관련하는피시험메모리로부터판독되는판독데이터의타이밍과합치시킬수가있다.

60. 发明授权

KR100238933B1 시험 패턴 발생기 失效
标题翻译：测试图形发生器
公开(公告)号：KR100238933B1
公开(公告)日：2000-03-02
申请号：KR1019960706236
申请日：1996-01-12
申请人： 가부시키가이샤 아드반테스트
发明人： 츠토마사루
IPC分类号： G11C29/00
CPC分类号： G01R31/31928 , G01R31/31813 , G01R31/31919 , G01R31/3193 , G11C29/56
摘要： 본 발명은 비트마다의 기록 인에이블/디스에이블 제어 가능 피시험 메모리를 시험할 경우에 임의의 초기치에 대하여 기대치를 용이하게 발생할 수 있는 시험 패턴 발생기를 제공한다. 이를 위해서, 명령 메모리(112)로부터의 신호에 의해 제어신호를 발생하는 XOR 제어기(131)를 설치한다. 그리고, 이 XOR 제어기(131)의 출력 신호를 한쪽 입력 단자에 받고, 다른쪽 입력 단자에 데이타 발생기 B(15)의 출력 반전 신호를 받는 앤드게이트(123)를 설치한다. 그리고 이 앤드게이트(123)의 출력을 한쪽 입력 단자에 받고, 다른쪽 입력 단자에 데이타 발생기 A(14)의 출력 신호를 받는 배타적 논리합 게이트(121)를 설치하여 시험 패턴 발생기를 구성한다.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式