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51. 发明授权

KR100472006B1 모스 트랜지스터 제조 방법 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：KR100472006B1
公开(公告)日：2005-03-10
申请号：KR1020020061429
申请日：2002-10-09
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , H01L21/76828 , H01L21/76829
摘要： 모스 트랜지스터 제조 방법에 관한 것으로, 그 목적은 PECVD에 의해 형성한 실리콘나이트라이드막 상에 SACVD에 의해 BPSG막을 형성할 때 붕소이온이 발생하여 이후 실리콘웨이퍼로 침투하는 것을 방지하는 데 있다. 이를 위해 본 발명에서는 BPSG막 증착 전에 오존으로 실리콘나이트라이드막을 표면처리하는 것을 특징으로하며, 따라서, 본 발명에 따른 모스 트랜지스터 제조 방법은, 필드 산화막에 의해 정의된 소자 영역에 측벽을 가진 게이트 전극, 소스 및 드레인을 포함하는 모스 트랜지스터 소자가 형성된 실리콘 기판의 상부에서, 게이트 전극, 소스 및 드레인 영역의 실리콘 상에 티타늄실리사이드를 형성하는 단계; 실리콘 기판의 상부 전면에 실리콘나이트라이드막을 형성하는 단계; 실리콘나이트라이드막을 오존 처리하는 단계; 및 오존 처리된 실리콘나이트라이드막 상에 BPSG막을 형성하는 단계를 포함하여 이루어진다.

52. 发明公开

KR1020050015665A 반도체 소자의 식각 정지막 제조 방법 失效
标题翻译：在半导体器件中形成蚀刻层的方法以防止氮化硅层渗透
公开(公告)号：KR1020050015665A
公开(公告)日：2005-02-21
申请号：KR1020030054600
申请日：2003-08-07
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/20
摘要： PURPOSE: A method of forming an etch stop layer in a semiconductor device is provided to prevent permeation of H into a silicon nitride layer by using SiCl4 as a silicon source. CONSTITUTION: A semiconductor device is formed on a silicon substrate(200). An etch stop layer is formed by depositing a silicon nitride on an upper surface of the semiconductor device by an atomic layered deposition method using a silicon source of SiCl4(202) and nitrogen sources of NH3(204) and N2O(206). An interlayer dielectric is formed on the etch stop layer. A contact electrode connected to an active region of the semiconductor device is formed through a contact hole which is formed by etching the interlayer dielectric and the etch stop layer.
摘要翻译：目的：提供一种在半导体器件中形成蚀刻停止层的方法，以通过使用SiCl 4作为硅源来防止H渗透到氮化硅层中。构成：半导体器件形成在硅衬底（200）上。通过使用SiCl 4（202）的硅源和NH 3（204）和N 2 O（206）的氮源的原子层状沉积方法在半导体器件的上表面上沉积氮化硅来形成蚀刻停止层。在蚀刻停止层上形成层间电介质。通过蚀刻层间电介质和蚀刻停止层形成的接触孔形成连接到半导体器件的有源区的接触电极。

53. 发明公开

KR1020040064117A 반도체 소자의 트렌치 형성 방법 失效
标题翻译：形成半导体器件的光束的方法
公开(公告)号：KR1020040064117A
公开(公告)日：2004-07-16
申请号：KR1020030001410
申请日：2003-01-09
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： PURPOSE: A method for forming a trench of a semiconductor device is provided to make the inside of a trench completely filled with a field oxide layer, by implanting oxygen ions into a silicon substrate, by thermally diffusing the oxygen ions to form a silicon oxide and by etching the silicon substrate and the silicon oxide to form the trench. CONSTITUTION: A pad oxide layer(12) and a silicon nitride layer(13) are formed on a semiconductor substrate(11). The silicon nitride layer and the pad oxide layer on a trench formation region are selectively etched. Oxygen ions are implanted into the semiconductor substrate in the trench formation region. The oxygen ions are thermally diffused to react with the semiconductor substrate so that an oxide is formed in the semiconductor substrate. The semiconductor substrate and the oxide in the trench formation region are etched to form the trench by using the silicon nitride layer as a mask. A liner oxide layer(17) is formed on the inner wall of the trench by a thermal diffusion process.
摘要翻译：目的：提供一种用于形成半导体器件的沟槽的方法，通过将氧离子注入硅衬底中，通过将氧离子热扩散以形成氧化硅，使沟槽的内部完全充满场氧化物层，并且通过蚀刻硅衬底和氧化硅以形成沟槽。构成：在半导体衬底（11）上形成衬垫氧化物层（12）和氮化硅层（13）。选择性地蚀刻沟槽形成区上的氮化硅层和衬垫氧化物层。在沟槽形成区域中将氧离子注入到半导体衬底中。氧离子被热扩散以与半导体衬底反应，从而在半导体衬底中形成氧化物。通过使用氮化硅层作为掩模，蚀刻半导体衬底和沟槽形成区域中的氧化物以形成沟槽。通过热扩散工艺在沟槽的内壁上形成衬里氧化物层（17）。

54. 发明公开

KR1020040055360A 플래쉬 메모리의 제조방법 无效
标题翻译：用于制作闪存的方法
公开(公告)号：KR1020040055360A
公开(公告)日：2004-06-26
申请号：KR1020020082004
申请日：2002-12-20
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L27/115
CPC分类号： H01L29/66553 , H01L21/28273 , H01L29/42336 , H01L29/66621 , H01L29/66825 , H01L29/7834
摘要： PURPOSE: A method for fabricating a flash memory is provided to make only a control gate and a transistor remain on a silicon substrate by forming a floating gate inside the silicon substrate. CONSTITUTION: A photoresist pattern is formed on the silicon substrate(11). Based upon the photoresist pattern, an etch process is performed to form a trench on the silicon substrate. After the photoresist pattern is eliminated, a tunneling oxide(14) is grown on the silicon substrate corresponding to the bottom of the trench by a thermal oxide process. Floating gate polysilicon is deposited to fill the trench. The floating gate polysilicon is planarized to have the same step as the silicon substrate so that the floating gate(15a) is formed. A dielectric layer(16) is formed on the floating gate and the silicon substrate. Control gate polysilicon to function as a substantial electrode is deposited on the dielectric layer to form a control gate(17). A photolithography process for defining a gate(18) is performed to etch the control gate and the dielectric layer at a time so that the gate is formed. An oxide process is performed on the defined gate to oxidize the periphery of the gate. Silicon nitride is deposited and is etched to form a sidewall(19) without a photolithography process. An ion implantation process for forming a source/drain(20,21) is performed.
摘要翻译：目的：提供一种制造闪速存储器的方法，以便通过在硅衬底内部形成浮置栅极而仅使控制栅极和晶体管保持在硅衬底上。构成：在硅衬底（11）上形成光刻胶图形。基于光致抗蚀剂图案，执行蚀刻工艺以在硅衬底上形成沟槽。在消除光致抗蚀剂图案之后，通过热氧化工艺在对应于沟槽底部的硅衬底上生长隧道氧化物（14）。沉积浮栅多晶硅以填充沟槽。浮置栅极多晶硅被平坦化以具有与硅衬底相同的步骤，从而形成浮置栅极（15a）。在浮置栅极和硅衬底上形成介电层（16）。用作基本电极的控制栅极多晶硅沉积在电介质层上以形成控制栅极（17）。执行用于限定栅极（18）的光刻工艺以一次蚀刻控制栅极和电介质层，从而形成栅极。在限定的栅极上进行氧化处理以氧化栅极的周边。沉积氮化硅并且被蚀刻以形成侧壁（19）而不进行光刻工艺。执行用于形成源极/漏极（20,21）的离子注入工艺。

55. 发明公开

KR1020040055357A 반도체 소자의 게이트 형성방법 失效
标题翻译：用于形成半导体器件栅极的方法
公开(公告)号：KR1020040055357A
公开(公告)日：2004-06-26
申请号：KR1020020082001
申请日：2002-12-20
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28123
摘要： PURPOSE: A method for forming a gate of a semiconductor device is provided to reduce the size of a semiconductor device by overlapping photoresist patterns with a time lag and by embodying a gate of an ultra-fine line width in the overlapped portion. CONSTITUTION: A gate oxide(12) is formed on a silicon substrate(11). After polysilicon(13) to be used as a gate electrode is deposited, a mask thin film(14) to be used as a hardening mask in a gate etch process is formed. The first photoresist pattern is formed on the mask thin film. An etch process is performed to etch the mask thin film. After the first photoresist pattern is removed, the second photoresist pattern(16) is formed on a part of the remaining mask thin film after the etch process and on the polysilicon. The mask thin film is etched based upon the second photoresist pattern. After the second photoresist pattern is eliminated, the polysilicon is etched by using the mask thin film partially left on the polysilicon. The mask thin film left on the polysilicon is removed to form the gate.
摘要翻译：目的：提供一种用于形成半导体器件的栅极的方法，以通过使光刻胶图案与时间延迟重叠并通过在重叠部分中实现超细线宽度的栅极来减小半导体器件的尺寸。构成：在硅衬底（11）上形成栅氧化层（12）。在沉积用作栅电极的多晶硅（13）之后，形成在栅极蚀刻工艺中用作硬化掩模的掩模薄膜（14）。第一光致抗蚀剂图案形成在掩模薄膜上。执行蚀刻工艺以蚀刻掩模薄膜。在去除第一光致抗蚀剂图案之后，在蚀刻工艺之后和多晶硅上，在剩余的掩模薄膜的一部分上形成第二光致抗蚀剂图案（16）。基于第二光致抗蚀剂图案蚀刻掩模薄膜。在消除第二光致抗蚀剂图案之后，通过使用部分留在多晶硅上的掩模薄膜来蚀刻多晶硅。留在多晶硅上的掩模薄膜被去除以形成栅极。

56. 发明公开

KR1020040055355A 박막 커패시터 및 그 제조 방법 失效
标题翻译：薄膜电容器及其制造方法
公开(公告)号：KR1020040055355A
公开(公告)日：2004-06-26
申请号：KR1020020081999
申请日：2002-12-20
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L27/108
摘要： PURPOSE: A thin film capacitor is provided to avoid a leakage current by separating the first electrode layer and the second electrode layer by a desired interval with respect to a dielectric layer. CONSTITUTION: The first electrode layer(M1) is formed on a lower insulation layer(52) formed on a semiconductor substrate(51). A capacitor region of a predetermined width is formed on the first electrode layer. A sidewall(57) is formed on the inner wall of the capacitor region. A dielectric layer(58) of a predetermined width is formed on the sidewall and the capacitor opening. The second electrode layer(M2) is formed on the dielectric layer. An interlayer dielectric(63) is formed on the lower insulation layer including the second and first electrode layers, having a via(200) exposing a predetermined portion of the second and first electrode layers. The via is filled with a metal material.
摘要翻译：目的：提供薄膜电容器，以通过相对于电介质层分离第一电极层和第二电极层所需的间隔来避免泄漏电流。构成：第一电极层（M1）形成在形成在半导体衬底（51）上的下绝缘层（52）上。在第一电极层上形成预定宽度的电容器区域。在电容器区域的内壁上形成侧壁（57）。在侧壁和电容器开口上形成有预定宽度的电介质层（58）。第二电极层（M2）形成在电介质层上。在包括第二电极层和第一电极层的下绝缘层上形成层间电介质（63），其具有暴露第二电极层和第一电极层的预定部分的通孔（200）。通孔填充有金属材料。

57. 发明公开

KR1020040032335A 모스 트랜지스터 제조 방법 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：KR1020040032335A
公开(公告)日：2004-04-17
申请号：KR1020020061429
申请日：2002-10-09
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , H01L21/76828 , H01L21/76829
摘要： PURPOSE: A method for manufacturing an MOS(Metal Oxide Semiconductor) transistor is provided to be capable of preventing boron ions from penetrating into a silicon substrate under a BPSG(Boron Phosphorous Silicate Glass) layer forming process. CONSTITUTION: An MOS transistor is formed on the predetermined portion of a silicon substrate(21). At this time, the MOS transistor includes a gate electrode(24), and a source/drain(27). A titanium silicide layer(28) is formed on the gate electrode and the source/drain, respectively. A silicon nitride layer(29) is formed on the entire surface of the resultant structure. An ozone treatment is performed on the silicon nitride layer. A BPSG(Boron Phosphorous Silicate Glass) layer(30) is then formed on the silicon nitride layer.
摘要翻译：目的：提供一种用于制造MOS（金属氧化物半导体）晶体管的方法，以能够在BPSG（硼磷酸硅酸盐玻璃）层形成工艺下防止硼离子渗透到硅衬底中。构成：在硅衬底（21）的预定部分上形成MOS晶体管。此时，MOS晶体管包括栅电极（24）和源极/漏极（27）。在栅极电极和源极/漏极上分别形成硅化钛层（28）。在所得结构的整个表面上形成氮化硅层（29）。在氮化硅层上进行臭氧处理。然后在氮化硅层上形成BPSG（硼磷酸硅酸盐玻璃）层（30）。

58. 发明公开

KR1020040029868A 반도체 소자 제조 방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020040029868A
公开(公告)日：2004-04-08
申请号：KR1020020060306
申请日：2002-10-02
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/28
CPC分类号： H01L21/76834 , H01L21/76807
摘要： PURPOSE: A method for fabricating a semiconductor device is provided to reduce total capacitance and improve the flow of current by forming simultaneously a wiring hole and a via hole using a difference between etching ratios of an SiC layer and an interlayer dielectric. CONSTITUTION: An interlayer dielectric(15) is formed on an entire surface of a semiconductor substrate structure(11) including a bottom wire(13). A barrier layer(14) is formed on the interlayer dielectric(15). An etching ratio of the barrier layer(14) is lower than the etching ratio of the interlayer dielectric. The interlayer dielectric formed on the bottom wire(13) is partially exposed by etching selectively the barrier layer. A photoresist pattern is formed on the barrier layer(14) to expose the barrier layer adjacent to the exposed interlayer dielectric. A wiring hole and a via hole are formed by etching the exposed barrier layer and the interlayer dielectric. The via hole and the wiring hole are buried by forming a copper layer(17) on the via hole, the wiring hole, and the barrier layer. The interlayer dielectric is exposed by performing a CMP process.
摘要翻译：目的：提供一种用于制造半导体器件的方法，通过使用SiC层和层间电介质的蚀刻比之间的差异同时形成布线孔和通孔来减少总电容并改善电流。构成：在包括底线（13）的半导体衬底结构（11）的整个表面上形成层间电介质（15）。在层间电介质（15）上形成阻挡层（14）。阻挡层（14）的蚀刻率比层间电介质的蚀刻率低。通过选择性地蚀刻阻挡层，在底部导线（13）上形成的层间电介质部分露出。在阻挡层（14）上形成光致抗蚀剂图案，以暴露与暴露的层间电介质相邻的阻挡层。通过蚀刻暴露的阻挡层和层间电介质来形成布线孔和通孔。通孔和布线孔通过在通孔，布线孔和阻挡层上形成铜层（17）而被掩埋。通过执行CMP工艺来暴露层间电介质。

59. 发明公开

KR1020040011252A 반도체 소자 및 그 제조 방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020040011252A
公开(公告)日：2004-02-05
申请号：KR1020020045024
申请日：2002-07-30
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L27/04
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to be capable of improving the degree of integration of an upper metal line, preventing the malfunction of the device caused by the thickness change of a dielectric layer, and increasing the capacitance of a capacitor. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate(21), a lower metal line(23) and a lower insulating layer(22) formed at the upper portion of the semiconductor substrate structure, and an interlayer dielectric(24) formed at the upper portion of the resultant structure. At this time, the interlayer dielectric includes an electrode hole(201). The semiconductor device further includes the first electrode layer(25) having a predetermined thickness, formed along the inner wall of the electrode hole, a pair of dielectric layers(26,27) formed at the upper portion of the first electrode layer, and the second electrode layer filled in the electrode hole. Preferably, an upper metal line is partially formed at the upper portion of the second electrode layer.
摘要翻译：目的：提供一种半导体器件及其制造方法，其能够提高上部金属线的集成度，防止由电介质层的厚度变化引起的器件的故障，并增加电容器的电容。构成：半导体器件设置有形成在半导体衬底结构的上部的半导体衬底（21），下部金属线（23）和下部绝缘层（22），以及形成在半导体衬底所得结构的上部。此时，层间电介质包括电极孔（201）。半导体器件还包括沿着电极孔的内壁形成的具有预定厚度的第一电极层（25），形成在第一电极层的上部的一对电介质层（26,27），以及第二电极层填充在电极孔中。优选地，上部金属线部分地形成在第二电极层的上部。

60. 发明授权

KR100325606B1 반도체 소자의 격리구조 및 그 제조방법 失效
标题翻译：半导体器件的隔离结构及其制造方法
公开(公告)号：KR100325606B1
公开(公告)日：2002-02-25
申请号：KR1019990021188
申请日：1999-06-08
申请人： 동부일렉트로닉스 주식회사
发明人： 박건욱
IPC分类号： H01L21/76
摘要： 반도체소자의격리구조및 그제조방법에관한것으로, 반도체기판의상면에산화막을형성하는공정과; 상기산화막의소정영역을소정깊이제1차식각하는공정과; 상기제1차식각된산화막의일부분을제2차식각하여반도체기판을노출시킴으로써잔존하는산화막을필드영역으로정의하는공정과; 상기노출된반도체기판을포함하여상기제1차또는제2차식각된산화막의상부에다결정실리콘층을형성하는공정과; 상기다결정실리콘층을재결정화시킴으로써상기재결정화된다결정실리콘층을활성영역으로정의하는공정을순차적으로실시하여본 발명에따른반도체소자의격리구조를제조함으로써, 고집적도에서도이웃하는소자들을전기적으로완전히격리시켜래치업과기생캐패시턴스의발생을제거하며, 이로인해소자의구동속도를향상시키고소비전력을감소시킨다.

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