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41. 发明公开

KR1020100081559A 비휘발성 메모리 장치 및 그 동작 방법 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：KR1020100081559A
公开(公告)日：2010-07-15
申请号：KR1020090000850
申请日：2009-01-06
申请人： 삼성전자주식회사
发明人： 설광수 , 박윤동 , 김석필
IPC分类号： G11C16/00 , H01L27/115 , G11C16/02
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3427 , G11C2213/71 , H01L27/0688 , H01L27/115 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L27/2463
摘要： PURPOSE: A nonvolatile memory device and a method for operating the same are provided to execute a program at each layer through a common source line. CONSTITUTION: A memory cell array(10) comprises a plurality of memory cell array layers. The memory cell array layer comprises a plurality of memory blocks(BLK0-BLKn). A layer decoder(20) selects a cell array layer from a memory cell array of a three dimensional structure according to address information. A row decoder(30) selects a memory block of the memory cell array according to the address information. The row decoder selects a word line of the selected memory block. A page buffer(40) temporarily stores data which is stored in the memory cell in an operation mode. The page buffer senses the data stored in the memory cells.
摘要翻译：目的：提供非易失性存储器件及其操作方法，以通过公共源极线在每一层执行程序。构成：存储单元阵列（10）包括多个存储单元阵列层。存储单元阵列层包括多个存储块（BLK0-BLKn）。层解码器（20）根据地址信息从三维结构的存储单元阵列中选择单元阵列层。行解码器（30）根据地址信息选择存储单元阵列的存储块。行解码器选择所选存储块的字线。页面缓冲器（40）在操作模式中临时存储存储在存储单元中的数据。页面缓冲区检测存储单元中存储的数据。

42. 发明授权

KR100968380B1 나노 스케일의 플래시 메모리, 나노 스케일의 와이어트랜지스터, 나노 스케일의 와이어 트랜지스터의 제조방법 및 교차형 와이어 장치의 크로스바 어레이 失效
标题翻译：分子线交叉闪光存储器
公开(公告)号：KR100968380B1
公开(公告)日：2010-07-09
申请号：KR1020047017351
申请日：2003-04-11
申请人： 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피.
发明人： 이튼쥬니어제임스알 , 퀘크스필립제이
IPC分类号： G11C16/00 , G11C11/34 , B82Y10/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0014 , G11C13/0023 , G11C2213/75 , G11C2213/77 , G11C2213/81 , H01L27/285 , H01L51/0052 , H01L51/0595 , Y10S977/943
摘要： 나노 스케일의 플래시 메모리는 (a) 반도체 물질을 포함하는 복수의 대략 평행한 제 1 와이어에 있으며, 채널 영역에 의해 분리되는 소스 및 드레인 영역과, (b) 반도체 물질 또는 금속을 포함하며, 채널 영역에 걸쳐서 0이 아닌 각도로 교차하는 복수의 대략 평행한 제 2 와이어에 있으며, 나노 스케일의 트랜지스터 어레이를 형성하는 게이트 전극과, (c) 제 1 와이어와 제 2 와이어의 각각의 교차점의 고온 전자 트랩 영역을 포함한다. 또한, 전압의 인가에 의해 설정될 수 있는 스위치 메모리 비트 또는 변경가능 트랜지스터를 형성할 수 있는 교차형 와이어 트랜지스터가 제공된다. 교차형 와이어 트랜지스터는 크로스바 어레이로 형성될 수 있다.

43. 发明公开

KR1020100075891A 자기 복구를 갖는 비휘발성 메모리 无效
标题翻译：具有自我恢复功能的非易失性存储器
公开(公告)号：KR1020100075891A
公开(公告)日：2010-07-05
申请号：KR1020107007383
申请日：2008-09-22
申请人： 샌디스크 테크놀로지스 엘엘씨
发明人： 쳉,스티븐,에스.
IPC分类号： G06F11/10 , G06F11/16 , G06F11/20 , G11C16/00
CPC分类号： G06F11/1666 , G06F11/20 , G11C29/74 , G11C29/765
摘要： A nonvolatile memory array includes two or more devices, each device containing data that is scrambled using a different scrambling scheme. When the same data is provided and stored in both devices, different data patterns occur in each device, so that if one of the patterns causes data pattern induced errors, the original data can be recreated from another copy that does not share the same data pattern.
摘要翻译：非易失性存储器阵列包括两个或更多个器件，每个器件包含使用不同的加扰方案加扰的数据。当相同的数据被提供并存储在两个设备中时，在每个设备中出现不同的数据模式，使得如果其中一个模式导致数据模式引起的错误，则可以从不共享相同数据模式的另一个副本重新创建原始数据。

44. 发明公开

KR1020100068923A 반도체 메모리 시스템의 제조 방법 有权
标题翻译：半导体存储器系统的制造方法
公开(公告)号：KR1020100068923A
公开(公告)日：2010-06-24
申请号：KR1020080127440
申请日：2008-12-15
申请人： 삼성전자주식회사
发明人： 장준호 , 정운재 , 안흥준
IPC分类号： G11C16/00 , G11C13/02
CPC分类号： G06F9/4401 , H01L27/115
摘要： PURPOSE: A manufacturing method of a semiconductor memory system is provided to improve the reliability of the semiconductor memory system by storing data in the variable resistance memory device. CONSTITUTION: A system code is stored in a first nonvolatile memory(S110). The first nonvolatile memory and the second nonvolatile memory are assembled(S120). The system code stored in the first nonvolatile memory is duplicated in the second nonvolatile memory(S130). The system code stored in the first nonvolatile memory is deleted. A duplication flag indicating that the system code stored in the first nonvolatile memory is duplicated in second nonvolatile memory is updated.
摘要翻译：目的：提供半导体存储器系统的制造方法，通过将数据存储在可变电阻存储器件中来提高半导体存储器系统的可靠性。构成：系统码存储在第一非易失性存储器中（S110）。组装第一非易失性存储器和第二非易失性存储器（S120）。存储在第一非易失性存储器中的系统代码被复制在第二非易失性存储器中（S130）。存储在第一非易失性存储器中的系统代码被删除。指示存储在第一非易失性存储器中的系统代码被复制在第二非易失性存储器中的复制标志被更新。

45. 发明公开

KR1020100063631A 플래시 메모리 기반의 차량 정보 저장 방법 및 장치 有权
标题翻译：用于存储闪存上的黑盒数据的方法和装置
公开(公告)号：KR1020100063631A
公开(公告)日：2010-06-11
申请号：KR1020090041381
申请日：2009-05-12
申请人： 한국전자통신연구원 , 아주대학교산학협력단
发明人： 이소연 , 윤현정 , 곽동용 , 김병국 , 최혁수 , 정태선
IPC分类号： G06Q50/30 , G11C16/00
CPC分类号： G06Q50/30 , G11C16/00
摘要： PURPOSE: A method and an apparatus for storing black-box data based on a flash memory are provided to store user information and vehicle information except driving information, thereby easily examining a cause of an accident. CONSTITUTION: A telematics terminal(150) receives vehicle information from one or more detecting devices. An information classifying device receives the vehicle information from the telematics terminal. The classified information identifies the kind of the received vehicle information. A volatile memory stores the vehicle information in an information storage area allocated to the identified kind. A nonvolatile memory stores the vehicle information saved in the information storage area.
摘要翻译：目的：提供一种用于存储基于闪速存储器的黑匣子数据的方法和装置，用于存储除了驾驶信息之外的用户信息和车辆信息，从而容易地检查事故的原因。构成：远程信息处理终端（150）从一个或多个检测设备接收车辆信息。信息分类装置从远程信息处理终端接收车辆信息。分类信息识别所接收的车辆信息的种类。易失性存储器将车辆信息存储在分配给所识别的种类的信息存储区域中。非易失性存储器存储保存在信息存储区域中的车辆信息。

46. 发明公开

KR1020100059666A 비휘발성 메모리 장치 无效
标题翻译：非易失性存储器件
公开(公告)号：KR1020100059666A
公开(公告)日：2010-06-04
申请号：KR1020090068975
申请日：2009-07-28
申请人： 삼성전자주식회사
发明人： 후지와라다이스케
IPC分类号： G11C16/00 , G11C16/06 , G11C16/32
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26
摘要： PURPOSE: A nonvolatile memory device is provided to reduce a memory operation time by controlling a preparation sequence and a stress sequence of an operating sequence in parallel. CONSTITUTION: A command generator(30) generates commands for executing a memory operation. A command buffer(20) stores the generated commands temporally. A preparation state unit executes a preparation sequence. The stress state unit executes the stress sequence. A logic unit controls an inner operation sequence. The internal operation controller(10) controls the sequence of the internal operation to execute the commands which are stored in the command buffer.
摘要翻译：目的：提供非易失性存储器件，通过并行地控制操作序列的制备顺序和应力序列来减少存储器操作时间。构成：命令生成器（30）生成用于执行存储器操作的命令。命令缓冲器（20）在时间上存储所生成的命令。准备状态单元执行准备序列。应力状态单元执行应力序列。逻辑单元控制内部操作序列。内部操作控制器（10）控制内部操作的顺序来执行存储在命令缓冲器中的命令。

47. 发明公开

KR1020100058825A 저항체를 이용한 반도체 장치, 이를 이용한 카드 또는 시스템 및 상기 반도체 장치의 구동 방법 无效
标题翻译：使用可变电阻元件的半导体器件，使用其的卡或系统和操作方法的半导体器件
公开(公告)号：KR1020100058825A
公开(公告)日：2010-06-04
申请号：KR1020080117377
申请日：2008-11-25
申请人： 삼성전자주식회사
发明人： 박준민 , 이광진 , 조백형
IPC分类号： G11C13/02 , G11C16/00
CPC分类号： G11C13/0069 , G11C15/046 , G11C2013/0076
摘要： PURPOSE: A semiconductor device using a variable resistive element is provided to prevent a malfunction by making a write address invalid when an input write address and a valid write address are identical. CONSTITUTION: A memory cell array(102) comprises a plurality of nonvolatile memory cells. A write buffer(132) stores a plurality of data which are written in the memory cell array. A write address buffer(124) stores a plurality of write addresses. A data output buffer selectively outputs data read from the memory cell array or the write buffer. A by-pass enable circuit(120) controls data output buffer according to whether an input write address and a valid write address are identical. An invalid unit(160) makes the write address stored in a write address buffer.
摘要翻译：目的：提供使用可变电阻元件的半导体器件，以便在输入写入地址和有效写入地址相同时，通过使写入地址无效来防止故障。构成：存储单元阵列（102）包括多个非易失性存储单元。写缓冲器（132）存储写入存储单元阵列的多个数据。写地址缓冲器（124）存储多个写地址。数据输出缓冲器选择性地输出从存储单元阵列或写入缓冲器读出的数据。旁路使能电路（120）根据输入写入地址和有效写入地址是否相同来控制数据输出缓冲器。无效单元（160）使写地址存储在写地址缓冲器中。

48. 发明公开

KR1020100047613A 플래시 메모리 장치 및 이의 테스트 방법 有权
标题翻译：闪存存储器件及其测试方法
公开(公告)号：KR1020100047613A
公开(公告)日：2010-05-10
申请号：KR1020080106589
申请日：2008-10-29
申请人： 삼성전자주식회사
发明人： 김보근 , 김대용 , 박준용
IPC分类号： G11C16/00 , G11C29/00
CPC分类号： G11C29/12 , G11C16/04 , G11C2029/1208 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/022
摘要： PURPOSE: A flash memory device and a testing method thereof are provided to reduce the time that it takes for testing without an additional design or a process change by transferring a test result signal to a test apparatus after testing each page. CONSTITUTION: An output node(NO) outputs a test result signal according to a pass or fail result of a column. A pre charge transistor is located between a corresponding bit line and an output node among the bit lines of the memory cell array. The pre charge transistor charges the bit line in advance with a voltage corresponding to the voltage level of the output node in the test mode in response to a pre charge control signal. A sensing node(SO) receives a voltage level corresponding to a bit value of the test data which is read from the bit line.
摘要翻译：目的：提供闪速存储器件及其测试方法，以便在测试每个页面之后，通过将测试结果信号传送到测试设备来减少测试所需的时间，而不需要额外的设计或过程改变。构成：输出节点（NO）根据列的通过或失败结果输出测试结果信号。预充电晶体管位于存储单元阵列的位线之间的相应位线和输出节点之间。预充电晶体管响应于预充电控制信号，以与测试模式中的输出节点的电压电平对应的电压预先对位线进行充电。感测节点（SO）接收对应于从位线读取的测试数据的位值的电压电平。

49. 发明公开

KR1020100042885A 비휘발성 메모리 장치의 동작 방법 无效
标题翻译：用于操作非易失性存储器件的方法
公开(公告)号：KR1020100042885A
公开(公告)日：2010-04-27
申请号：KR1020080102087
申请日：2008-10-17
申请人： 삼성전자주식회사
发明人： 최영준 , 오상윤
IPC分类号： G11C16/00 , G11C7/10
CPC分类号： G06F13/18 , G06F12/0246 , G11C16/00
摘要： PURPOSE: An operation method of a non-volatile memory device is provided to improve the operation speed of a system by processing commands after determining a priority about commands. CONSTITUTION: Expected operation times for a plurality of commands are calculated based on estimated operation times for a plurality of commands received form a non-volatile memory device(S40). The priority about a plurality of commands is determined based on the expected operation times and a predetermined rule(S41). The expected operation times and a plurality of commands are transmitted to the non-volatile memory device based on the priority(S43). When a delay times and a delay time is over a predetermined criteria, a specific command is determined to a top priority. When addresses corresponding to a plurality of write commands are overlapped, a write command which is to be precedently executed is determined to be a higher priority than a write command which is to be executed later.
摘要翻译：目的：提供一种非易失性存储器件的操作方法，用于通过在确定关于命令的优先级之后处理命令来提高系统的操作速度。构成：基于从非易失性存储装置接收的多个命令的估计操作时间来计算多个命令的预期操作时间（S40）。基于预期操作时间和预定规则来确定关于多个命令的优先权（S41）。基于优先级将期望的操作时间和多个命令发送到非易失性存储器件（S43）。当延迟时间和延迟时间超过预定标准时，将特定命令确定为最高优先级。当与多个写入命令相对应的地址重叠时，将先前执行的写入命令确定为比稍后执行的写入命令更高的优先级。

50. 发明公开

KR1020100040931A 저항 변화 메모리 장치 및 그 프로그래밍 방법 失效
标题翻译：电阻变化存储器件及其编程方法
公开(公告)号：KR1020100040931A
公开(公告)日：2010-04-21
申请号：KR1020107003429
申请日：2008-06-25
申请人： 가부시끼가이샤 도시바
发明人： 도다하루끼 , 나까이히로또
IPC分类号： G11C13/00 , G11C16/00 , G11C13/02
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/31 , G11C2213/32
摘要： A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.
摘要翻译：一种对电阻变化存储器件进行编程的方法包括：将程序电压脉冲施加到存储器单元以编程目标电阻值; 设置各个编程电压脉冲之间的热弛豫时间; 并且根据由先前的编程电压脉冲应用确定的当前单元的电阻值来控制每个编程电压脉冲的形状。

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