专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明公开

KR1020040001891A 반도체 장치의 캐패시터 제조방법 无效
标题翻译：制造半导体器件电容器的方法
公开(公告)号：KR1020040001891A
公开(公告)日：2004-01-07
申请号：KR1020020037225
申请日：2002-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 김남경 , 염승진
IPC分类号： H01L21/8242
摘要： PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of improving reliability by forming a nitride layer on a capacitor insulating layer. CONSTITUTION: A lower electrode(24) is formed on a substrate(20) having a contact plug(23). A capacitor insulating layer(25) is formed on the resultant structure. The capacitor insulating layer(25) is planarized to expose the lower electrode(24). A nitride layer(26) is formed on the capacitor insulating layer by plasma activation energy using NH3 or N2 gas. A dielectric film(27) is formed on the lower electrode. An upper electrode(28) is formed on the dielectric film.
摘要翻译：目的：提供一种制造半导体器件的电容器的方法，其能够通过在电容器绝缘层上形成氮化物层来提高可靠性。构成：在具有接触插塞（23）的基板（20）上形成下电极（24）。在所得结构上形成电容器绝缘层（25）。将电容器绝缘层25平坦化，露出下部电极24。通过使用NH 3或N 2气体的等离子体活化能，在电容器绝缘层上形成氮化物层（26）。电介质膜（27）形成在下电极上。在电介质膜上形成上电极（28）。

42. 发明授权

KR100393965B1 반도체 소자의 캐패시터 및 그의 제조 방법 失效
标题翻译： 반도체소자의캐패시터및그의제조방법
公开(公告)号：KR100393965B1
公开(公告)日：2003-08-06
申请号：KR1020000079564
申请日：2000-12-21
申请人： 에스케이하이닉스 주식회사
发明人： 권순용 , 염승진
IPC分类号： H01L21/28
摘要： PURPOSE: A capacitor and a method for manufacturing the same are provided to simplify manufacturing processes without using a glue layer by completely filling a metal film into a plug. CONSTITUTION: An interlayer dielectric having a contact hole is formed on a semiconductor substrate. A polysilicon plug is partially filled into the contact hole. A metal barrier is formed on the polysilicon plug. A first lower electrode(28) and a second lower electrode(29) are sequentially formed on the metal barrier, thereby completely filling the contact hole. The first and second lower electrodes(28,29) are composed of Ir or Ru and IrOx or RuOx, respectively. Then, a dielectric film and an upper electrode are sequentially formed on the resultant structure.
摘要翻译：目的：提供一种电容器及其制造方法，以通过将金属膜完全填充到插塞中而不使用胶层来简化制造工艺。构成：在半导体基板上形成具有接触孔的层间绝缘膜。多晶硅塞部分填充到接触孔中。金属屏障形成在多晶硅插塞上。在金属屏障上依次形成第一下电极（28）和第二下电极（29），从而完全填充接触孔。第一和第二下电极（28,29）分别由Ir或Ru和IrOx或RuOx组成。然后，在所得到的结构上依次形成电介质膜和上电极。

43. 发明公开

KR1020030054054A 강유전체 메모리소자의 캐패시터 제조방법 无效
标题翻译：用于制造电介质存储器件电容器的方法
公开(公告)号：KR1020030054054A
公开(公告)日：2003-07-02
申请号：KR1020010084145
申请日：2001-12-24
申请人： 에스케이하이닉스 주식회사
发明人： 김남경 , 염승진
IPC分类号： H01L27/105
摘要： PURPOSE: A method for manufacturing a capacitor of a ferroelectric memory device is provided to prevent degradation of a plug by using two-step annealing for forming a ferroelectric film. CONSTITUTION: A lower electrode(9) is formed on a semiconductor substrate(0). A BLT dielectric film(10) is formed on the lower electrode(9). A plasma treatment is performed to the BLT dielectric film(10). The plasma treated BLT dielectric film(10) is then annealed. At this time, the annealing temperature is higher than that of the plasma treatment. An upper electrode is then formed on the BLT dielectric film(10). The temperature of the plasma treatment is 200-400°C, and the temperature of the annealing is 550-800°C.
摘要翻译：目的：提供一种用于制造铁电存储器件的电容器的方法，以通过使用用于形成铁电体膜的两步退火来防止插头的劣化。构成：在半导体衬底（0）上形成下电极（9）。在下电极（9）上形成BLT电介质膜（10）。对BLT电介质膜（10）进行等离子体处理。然后等离子体处理的BLT介电膜（10）退火。此时，退火温度高于等离子体处理温度。然后在BLT电介质膜（10）上形成上电极。等离子体处理的温度为200-400℃，退火温度为550-800℃。

44. 发明授权

KR100388465B1 루테늄 하부전극을 갖는 강유전체 캐패시터 및 그 형성방법 失效
标题翻译： 루테늄하부전극을갖는강유전체캐패시터및그형성방루
公开(公告)号：KR100388465B1
公开(公告)日：2003-06-25
申请号：KR1020010038679
申请日：2001-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 김남경 , 염승진
IPC分类号： H01L27/105
摘要： PURPOSE: A ferroelectric capacitor having a ruthenium bottom electrode and a method for forming the same are provided to prevent the generation of ruthenium oxide on a surface of the ruthenium bottom electrode by improving a process for forming the ruthenium bottom electrode. CONSTITUTION: An isolation layer(11), a word line(13), a bit line(16) are formed on a silicon substrate(10). A bottom electrode contact hole is formed by etching selectively interlayer dielectrics(15,17). A polysilicon plug(18), a silicide layer(19), and a barrier metal layer(20) are formed inside the bottom electrode contact hole. A ruthenium layer(21) for a bottom electrode is formed on an entire surface of the silicon substrate(10). A ruthenium tungsten nitride layer(22) is formed on the ruthenium layer(21). A ferroelectric layer(23) is formed on the ruthenium tungsten nitride layer(22). A conductive layer(24) for an upper electrode is formed on the ferroelectric layer(23).
摘要翻译：目的：提供具有钌底电极的铁电电容器及其形成方法，以通过改进形成钌底电极的工艺来防止在钌底电极的表面上产生氧化钌。构成：在硅衬底（10）上形成隔离层（11），字线（13），位线（16）。通过选择性蚀刻层间介质（15,17）形成底部电极接触孔。多晶硅插塞（18），硅化物层（19）和阻挡金属层（20）形成在底部电极接触孔内。在硅衬底（10）的整个表面上形成用于底部电极的钌层（21）。在钌层（21）上形成钌氮化钨层（22）。在钌氮化钨层（22）上形成铁电层（23）。在铁电层（23）上形成用于上电极的导电层（24）。

45. 发明公开

KR1020030003354A 루테늄 하부전극을 갖는 강유전체 캐패시터 및 그 형성방법 失效
标题翻译：具有真空底电极的电解电容器及其形成方法
公开(公告)号：KR1020030003354A
公开(公告)日：2003-01-10
申请号：KR1020010038677
申请日：2001-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 김남경 , 염승진
IPC分类号： H01L27/105
摘要： PURPOSE: A ferroelectric capacitor having a ruthenium bottom electrode and a method for forming the same are provided to improve reliability and a yield of a semiconductor device by preventing the generation of a ruthenium oxide on a boundary between the ruthenium bottom electrode and a ferroelectric layer. CONSTITUTION: An isolation layer(11), a word line(13), a bit line(16) are formed on a silicon substrate(10). A bottom electrode contact hole is formed by etching selectively interlayer dielectrics(15,17). A polysilicon plug(18), a silicide layer(19), and a barrier metal layer(20) are formed inside the bottom electrode contact hole. A ruthenium layer(21) for a bottom electrode is formed on the silicon substrate(10). A lithium oxide layer(22) is formed on the ruthenium layer(21). A ferroelectric layer(23) is formed on the lithium oxide layer(22). A conductive layer(24) for an upper electrode is formed on the ferroelectric layer(23).
摘要翻译：目的：提供具有钌底电极的铁电电容器及其形成方法，以通过防止在钌底电极和铁电体层之间的边界上产生氧化钌来提高半导体器件的可靠性和产率。构成：在硅衬底（10）上形成隔离层（11），字线（13），位线（16）。通过蚀刻选择性层间电介质（15,17）形成底部电极接触孔。在底部电极接触孔内形成多晶硅插塞（18），硅化物层（19）和阻挡金属层（20）。在硅衬底（10）上形成用于底部电极的钌层（21）。在钌层（21）上形成氧化锂层（22）。在氧化锂层（22）上形成铁电体层（23）。在强电介质层（23）上形成用于上电极的导电层（24）。

46. 发明授权

KR100362185B1 반도체 소자의 강유전체 캐패시터 형성방법 失效
公开(公告)号：KR100362185B1
公开(公告)日：2002-11-23
申请号：KR1020000074493
申请日：2000-12-08
申请人： 에스케이하이닉스 주식회사
发明人： 김남경 , 염승진
IPC分类号： H01L27/105
摘要： 본 발명은 반도체 제조 기술에 관한 것으로, 특히 (Bi
x La
y )Ti
3 O
12 (이하, BLT라 함) 박막을 유전체로 사용하는 강유전체 캐패시터 형성 공정에 관한 것이며, BLT를 강유전체 박막으로 사용함에 있어서 BLT의 충분한 핵 생성을 통해 보다 치밀한 막질을 얻을 수 있는 반도체 소자의 강유전체 캐패시터 형성방법을 제공하는데 그 목적이 있다. 본 발명은 강유전체 캐패시터 형성방법에 있어서, 하부전극용 전도막이 형성된 기판 상에 액상의 비스무스-란탄-티타늄 산화막을 도포하는 제1 단계; 베이크 공정을 실시하여 상기 비스무스-란탄-티타늄 산화막을 박막화하는 제2 단계; NH
3 플라즈마 처리를 실시하여 상기 비스무스-란탄-티타늄 산화막 내의 금속 원소 및 용매와 결합된 유기물을 제거하는 제3 단계; 산소 플라즈마 처리를 실시하여 상기 비스무스-란탄-티타늄 산화막의 페로브스카이트 핵 생성을 유도하는 제4 단계; 상기 비스무스-란탄-티타늄 산화막에 대해 결정립 성장 열처리를 수행하는 제5 단계; 및 상기 비스무스-란탄-티타늄 산화막 상에 상부전극용 전도막을 형성하는 제6 단계를 포함하여 이루어진다.

47. 发明授权

KR100358137B1 기저 층간절연막으로서 수소확산 방지를 위한 티타늄산화막을 구비하는 강유전체 메모리 소자의 제조 방법 失效
标题翻译：制备具有氧化钛氢屏障的FeRAM作为层间电介质基底的方法
公开(公告)号：KR100358137B1
公开(公告)日：2002-10-25
申请号：KR1019990065827
申请日：1999-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 조광준 , 염승진 , 이상규
IPC分类号： H01L27/105
摘要： 본발명은금속배선간절연막형성및 페시베이션공정등과같이캐패시터형성후 실시되는후속공정에서발생하는수소에의한손상을억제하기위하여, 기저층간절연막으로서수소확산방지를위한티타늄산화막을구비하는강유전체메모리소자의제조방법에관한것으로, SBT(SrBiTaO) 등의강유전체막을이용한 FeRAM 소자제조에있어서강유전체캐패시터상부에형성되는금속배선간절연막및 페시베이션층형성공정에서발생하는수소에의한소자특성저하를방지하기위하여상기각 절연막의기저층으로티타늄산화막(TiO)을형성하는데특징이있다.

48. 发明公开

KR1020020050415A 반도체 소자의 캐패시터 및 그의 제조 방법 失效
标题翻译：半导体器件的电容器及其制造方法
公开(公告)号：KR1020020050415A
公开(公告)日：2002-06-27
申请号：KR1020000079564
申请日：2000-12-21
申请人： 에스케이하이닉스 주식회사
发明人： 권순용 , 염승진
IPC分类号： H01L21/28
摘要： PURPOSE: A capacitor and a method for manufacturing the same are provided to simplify manufacturing processes without using a glue layer by completely filling a metal film into a plug. CONSTITUTION: An interlayer dielectric having a contact hole is formed on a semiconductor substrate. A polysilicon plug is partially filled into the contact hole. A metal barrier is formed on the polysilicon plug. A first lower electrode(28) and a second lower electrode(29) are sequentially formed on the metal barrier, thereby completely filling the contact hole. The first and second lower electrodes(28,29) are composed of Ir or Ru and IrOx or RuOx, respectively. Then, a dielectric film and an upper electrode are sequentially formed on the resultant structure.
摘要翻译：目的：提供电容器及其制造方法，以通过将金属膜完全填充到插头中而简化制造工艺而不使用胶层。构成：在半导体衬底上形成具有接触孔的层间电介质。多孔插塞部分地填充到接触孔中。在多晶硅插塞上形成金属屏障。第一下电极（28）和第二下电极（29）依次形成在金属阻挡层上，从而完全填充接触孔。第一和第二下部电极（28,29）分别由Ir或Ru和IrOx或RuOx组成。然后，在所得到的结构上依次形成电介质膜和上电极。

49. 发明公开

KR1020020045158A 반도체 소자의 강유전체 캐패시터 형성방법 失效
标题翻译：形成半导体器件的电容器的方法
公开(公告)号：KR1020020045158A
公开(公告)日：2002-06-19
申请号：KR1020000074483
申请日：2000-12-08
申请人： 에스케이하이닉스 주식회사
发明人： 김남경 , 양우석 , 염승진
IPC分类号： H01L27/105
摘要： PURPOSE: A method for forming a ferroelectric capacitor of a semiconductor device is provided to improve the reliability of the device and the yield by reducing a thermal budget of a BLT thin film as a dielectric. CONSTITUTION: An element membrane separation(11), a word-line(12), and a bit-line(14) are formed on a silicon substrate(10). Interlayer dielectrics(13,15) are selectively etched to form a bottom electrode contact hole. A poly silicon plug(16) and a silicide /metal barrier layer(17) are formed within the contact hole. A bottom electrode(18) is formed. A BLT film(19) is coated on the upper part of the entire structure on which the bottom electrode is formed. After a baking process is performed, an oxygen plasma treatment is performed. Sequentially, a rapid thermal annealing process and a heat treatment using an electric furnace are performed. The oxygen plasma treatment is performed by using one of O2, N2O, H2O2, and O3. In the oxygen plasma treatment, a plasma power is in a range of 25 to 500W, a working pressure is in a range of 0.1mTorr to 10Torr, and a wafer temperature is in a range of 200 to 500 degrees.
摘要翻译：目的：提供一种用于形成半导体器件的铁电电容器的方法，通过降低作为电介质的BLT薄膜的热预算来提高器件的可靠性和产量。构成：在硅衬底（10）上形成元件膜分离（11），字线（12）和位线（14）。选择性地蚀刻层间电介质（13,15）以形成底电极接触孔。多孔硅插头（16）和硅化物/金属阻挡层（17）形成在接触孔内。形成底部电极（18）。在形成底部电极的整个结构的上部涂覆有BLT膜（19）。进行烘烤处理后，进行氧等离子体处理。接下来，进行快速热退火处理和使用电炉的热处理。氧等离子体处理通过使用O 2，N 2 O，H 2 O 2和O 3中的一种进行。在氧等离子体处理中，等离子体功率为25〜500W的范围，工作压力为0.1mTorr〜10Torr，晶圆温度为200〜500度的范围。

50. 发明授权

KR100329781B1 수소확산을 방지할 수 있는 강유전체 메모리 소자 제조 방법 有权
标题翻译：形成能够防止氢扩散的火炬的方法
公开(公告)号：KR100329781B1
公开(公告)日：2002-03-25
申请号：KR1019990025003
申请日：1999-06-28
申请人： 에스케이하이닉스 주식회사
发明人： 양우석 , 염승진 , 유용식
IPC分类号： H01L27/10
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/31616 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L27/1085
摘要： 본발명은금속배선간절연막및 페시베이션막형성시수소확산에의한강유전체특성저하를효과적으로방지할수 있는강유전체메모리소자제조방법에관한것으로, 금속배선간절연막및 페시베이션막형성전에 ALD법으로 AlO수소확산방지막을형성하는데그 특징이있다. 이러한방법은실란가스와플라즈마를사용하지않으므로수소원자, 이온및 분자발생이효과적으로억제되고 ALD법은일종의 CVD법이므로피복특성이우수하다.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式