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41. 发明公开

KR1020020003893A 반도체 소자의 제조방법 有权
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020020003893A
公开(公告)日：2002-01-16
申请号：KR1020000034318
申请日：2000-06-21
申请人： 에스케이하이닉스 주식회사
发明人： 김태균 , 장세억 , 여인석
IPC分类号： H01L21/316
摘要： PURPOSE: A method for fabricating a semiconductor device is provided to improve reliability of a semiconductor device by using an oxidation process instead of a self-aligned contact barrier layer formation process. CONSTITUTION: A field oxide layer(2) is formed on a silicon substrate(1). A thermal oxide layer is grown on the silicon substrate(1). A polysilicon layer is deposited on the thermal oxide layer and the field oxide layer(2). A hard mask layer is deposited on the polysilicon layer. A mask pattern is formed by patterning the hard mask. A sacrificial gate is formed on the silicon substrate(1) by performing an etching process. A screen oxide layer is formed on a sidewall of the sacrificial gate and the surface of the silicon substrate(1). An LDD(Lightly Doped Drain) region(12) is formed on the silicon substrate(1) of both sides of the sacrificial gate. A spacer(13) is formed by depositing and etching a spacer oxide layer thereon. A source/drain region(14) is formed on the silicon substrate(1) of both sides of the sacrificial gate. The first interlayer dielectric(15) is deposited on the whole surface. The first interlayer dielectric(15) is flattened and the sacrificial gate is exposed. A gate insulating layer and a tungsten layer are formed thereon. A tungsten gate(20) is formed by polishing the tungsten layer and the gate insulating layer. The second interlayer dielectric(22) is deposited on the whole surface. A contact hole(23) is formed by etching the second and the first interlayer dielectrics(22,15). A tungsten oxide layer(30) is formed by oxidizing the exposed tungsten gate.
摘要翻译：目的：提供一种用于制造半导体器件的方法，以通过使用氧化工艺代替自对准接触阻挡层形成工艺来提高半导体器件的可靠性。构成：在硅衬底（1）上形成场氧化物层（2）。在硅衬底（1）上生长热氧化层。多晶硅层沉积在热氧化物层和场氧化物层（2）上。在多晶硅层上沉积硬掩模层。通过图案化硬掩模形成掩模图案。通过进行蚀刻工艺在硅衬底（1）上形成牺牲栅极。在牺牲栅极的侧壁和硅衬底（1）的表面上形成屏蔽氧化物层。在牺牲栅极的两侧的硅衬底（1）上形成LDD（轻掺杂漏极）区域（12）。通过在其上沉积和蚀刻间隔氧化物层形成间隔物（13）。源极/漏极区域（14）形成在牺牲栅极两侧的硅衬底（1）上。第一层间电介质（15）沉积在整个表面上。第一层间电介质（15）被平坦化并且牺牲栅极被暴露。在其上形成栅极绝缘层和钨层。通过研磨钨层和栅极绝缘层来形成钨栅（20）。第二层间电介质（22）沉积在整个表面上。通过蚀刻第二层和第一层间电介质（22,15）形成接触孔（23）。通过氧化暴露的钨栅形成氧化钨层（30）。

42. 发明公开

KR1020020002629A 반도체소자의 미세패턴 형성방법 无效
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：KR1020020002629A
公开(公告)日：2002-01-10
申请号：KR1020000036855
申请日：2000-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/311
摘要： PURPOSE: A method for forming a fine pattern of a semiconductor device is provided to enable high integration, by using a selective epitaxial growth(SEG) silicon layer formed by using a SEG process. CONSTITUTION: An etch target layer is formed on a semiconductor substrate(31). A silicon-rich oxynitride layer(35) as a hard mask layer is formed on the etch target layer. The first chemical vapor deposition(CVD) oxide layer exposing a pattern region of the etch target layer is formed on the hard mask layer. A spacer made of the second CVD oxide layer is formed on the sidewall of the first CVD oxide layer. The silicon-rich oxynitride layer exposed between the second CVD oxide layers is grown to form a SEG silicon layer by a SEG method. The first and second CVD oxide layers are eliminated. The silicon-rich oxynitride layer is etched by using the SEG silicon layer as a mask. The etch target layer is etched by using the silicon-rich oxynitride layer as a mask while the SEG silicon layer is etched. An interlayer dielectric is formed by a subsequent process.
摘要翻译：目的：提供一种用于形成半导体器件的精细图案的方法，以通过使用通过使用SEG工艺形成的选择性外延生长（SEG）硅层来实现高集成度。构成：在半导体衬底（31）上形成蚀刻目标层。在蚀刻目标层上形成作为硬掩模层的富硅氧氮化物层（35）。暴露蚀刻目标层的图案区域的第一化学气相沉积（CVD）氧化物层形成在硬掩模层上。由第二CVD氧化物层制成的间隔物形成在第一CVD氧化物层的侧壁上。在第二CVD氧化物层之间暴露的富硅氧氮化物层通过SEG法生长以形成SEG硅层。消除第一和第二CVD氧化物层。通过使用SEG硅层作为掩模来蚀刻富硅氧氮化物层。通过使用富硅氧氮化物层作为掩模蚀刻蚀刻目标层，同时蚀刻SEG硅层。通过后续工艺形成层间电介质。

43. 发明授权

KR100318272B1 반도체 소자의 미세 패턴 형성방법 失效
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：KR100318272B1
公开(公告)日：2001-12-24
申请号：KR1019990060294
申请日：1999-12-22
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/3213
摘要： 본발명은라인과같은패턴의선폭제어가용이한반도체소자의미세패턴형성방법을개시하며, 개시된본 발명의반도체소자의미세패턴형성방법은, 반도체기판상에패터닝용박막, 하드마스크막, 실리콘막및 산화막을차례로형성하는단계; 상기실리콘막을노출시키는콘택홀이형성되도록, 상기산화막을패터닝하는단계; 상기콘택홀의측벽에스페이서를형성하는단계; 상기콘택홀에의해노출된실리콘막부분에실리콘에피층을성장시키는단계; 상기스페이서및 산화막을제거하는단계; 상기실리콘에피층을마스크로해서상기실리콘막과하드마스크막을식각하는단계; 및상기하드마스크막을마스크로해서, 상기패터닝용박막을식각하는단계를포함하여이루어진다.

44. 发明授权

KR100314810B1 대머신 게이트를 적용한 반도체 소자 제조방법 失效
标题翻译：一种用于制造用于镶嵌栅极的半导体器件的方法
公开(公告)号：KR100314810B1
公开(公告)日：2001-11-17
申请号：KR1019990065880
申请日：1999-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/336
摘要： 본발명은반도체제조기술에관한것으로, 특히대머신(damascene) 게이트를적용한반도체소자제조방법에관한것이다. 본발명은텅스텐을사용한대머신게이트를적용함에있어서, 후속콘택홀마스크공정시오정렬이발생하더라도단락을방지할수 있는즉, 공정마진을증대시킬수 있는대머신게이트를적용한반도체소자제조방법을제공하는데그 목적이있다. 본발명의특징적인반도체소자제조방법은, 소정의하부층이형성된실리콘기판상부의제1 층간절연막에매립된텅스텐대머신게이트구조를형성하는제1 단계; 상기제1 단계수행후, 전체구조상부에제2 층간절연막을형성하는제2 단계; 상기제1 및제2 층간절연막을선택식각하여상기실리콘기판및 상기텅스텐대머신게이트구조의텅스텐막을노출시키는콘택홀을형성하는제3 단계; 노출된상기텅스텐막을일정두께만큼산화시켜 WO막을형성하는제4 단계; 상기제4 단계에서노출된상기실리콘기판에형성된실리콘산화막을선택적으로제거하는제5 단계; 및상기콘택홀에콘택물질을매립하는제6 단계를포함하여이루어진다.

45. 发明公开

KR1020010065907A 반도체 소자의 듀얼-폴리실리콘 게이트 형성방법 无效
标题翻译：用于形成半导体器件的双嵌段多晶硅栅的方法
公开(公告)号：KR1020010065907A
公开(公告)日：2001-07-11
申请号：KR1019990066923
申请日：1999-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/336
摘要： PURPOSE: A method for forming a dual-implanted polysilicon gate is to ensure the concentration profile of a stable boron ion by preventing a dopant depletion and a dopant transmission in a polysilicon layer of a P-channel MOSFET region. CONSTITUTION: A gate insulating layer(21) is grown on a silicon substrate(20). A polysilicon layer(22) is formed on the gate insulating layer. A CoSi2 layer is deposited on the polysilicon layer. The first photoresist pattern is formed to coat a P-channel MOSFET region. Phosphorous is implanted into the exposed CoSi2 layer. After removing the first photoresist pattern, the second photoresist pattern is formed to coat N-channel MOSFET region. Boron is implanted into the exposed CoSi2 layer. After removing the second photoresist pattern, the entire structure is annealed to diffuse and activate the ion implanted dopants. After wet etching the CoSi2 layer, a WN layer(26) and a W layer(27) are deposited on the polysilicon layer. A gate electrode pattern is formed by selectively etching the W layer, the WN layer, and the polysilicon layer.
摘要翻译：目的：形成双注入多晶硅栅极的方法是通过防止P沟道MOSFET区域的多晶硅层中的掺杂剂消耗和掺杂剂透射来确保稳定的硼离子的浓度分布。构成：在硅衬底（20）上生长栅绝缘层（21）。在栅极绝缘层上形成多晶硅层（22）。 CoSi2层沉积在多晶硅层上。形成第一光致抗蚀剂图案以涂覆P沟道MOSFET区域。磷被植入到暴露的CoSi2层中。在去除第一光致抗蚀剂图案之后，形成第二光致抗蚀剂图案以涂覆N沟道MOSFET区域。硼被暴露在CoSi2层中。在去除第二光致抗蚀剂图案之后，整个结构被退火以扩散和激活离子注入的掺杂剂。在湿蚀刻CoSi 2层之后，在多晶硅层上沉积WN层（26）和W层（27）。通过选择性地蚀刻W层，WN层和多晶硅层来形成栅电极图案。

46. 发明公开

KR1020010058537A 대머신 게이트를 적용한 반도체 소자 제조방법 失效
标题翻译：使用DAMASCENE GATE制造半导体器件的方法
公开(公告)号：KR1020010058537A
公开(公告)日：2001-07-06
申请号：KR1019990065880
申请日：1999-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/336
摘要： PURPOSE: A method for manufacturing a semiconductor device using a damascene gate is provided to increase a process margin by using a tungsten damascene gate. CONSTITUTION: A structure of a damascene gate buried into the first interlayer dielectric(25) is formed on a silicon substrate(20). The second interlayer dielectric(28) is formed on the whole structure. A contact hole is formed to expose the silicon substrate(20) and a tungsten layer(27) of the tungsten damascene gate structure by etching selectively the first and the second interlayer dielectrics(25,28). A WO3 layer(29) is formed by oxidizing the exposed tungsten layer(27). The silicon oxide layer formed on the exposed silicon substrate(20) is removed selectively. A contact material is buried into the contact hole.
摘要翻译：目的：提供一种使用镶嵌栅极制造半导体器件的方法，以通过使用钨镶嵌栅极来增加工艺裕度。构成：在硅衬底（20）上形成埋在第一层间电介质（25）中的镶嵌栅极的结构。第二层间电介质（28）形成在整个结构上。通过选择性地蚀刻第一和第二层间电介质（25,28），形成接触孔以暴露钨镶嵌栅极结构的硅衬底（20）和钨层（27）。通过氧化暴露的钨层（27）形成WO3层（29）。形成在暴露的硅衬底（20）上的氧化硅层被选择性地去除。接触材料埋入接触孔中。

47. 发明授权

KR100293829B1 반도체 소자의 캐패시터 제조방법 失效
标题翻译：制造用于半导体器件的电容器的方法
公开(公告)号：KR100293829B1
公开(公告)日：2001-06-15
申请号：KR1019990012825
申请日：1999-04-12
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/283
摘要： 본발명은하부전극의하부구조층의산화를방지하여고집적화에대응하는캐패시터용량을확보함과더불어공정을단순화시킬수 있는반도체소자의캐패시터제조방법을제공한다. 본발명에따른반도체소자의캐패시터제조방법은상부에캐패시터용콘택홀을구비한절연막이형성된반도체기판을제공하는단계; 콘택홀에매립되도록상기절연막상에플러그용도전막을형성하는단계; 도전막을전면식각하여플러그를형성하는단계; 플러그상부에금속-실리사이드막을형성하는단계; 기판전면에티타늄이분산된백금막을형성하는단계; 티타늄이분산된백금막을패터닝하여금속-실리사이드막과콘택하는캐패시터의하부전극을형성하는단계; 및, 기판전면에유전체막및 캐패시터의상부전극용물질막을형성하는단계를포함한다. 본실시예에서, 티타늄이분산된백금막은티타늄이포함된혼합물타겟을이용하여백금막을스퍼터링방식으로증착하거나, 백금막을증착한후 상기백금막으로티타늄이온을이온주입하여형성하거나또는백금을포함한소오스와티타늄을포함한소오스를이용하여화학기상증착방식으로형성한다.

48. 发明公开

KR1020000044882A 반도체 소자의 쉘로우 트랜치 소자분리막 형성방법 无效
标题翻译：用于形成半导体器件的低温分离膜的方法
公开(公告)号：KR1020000044882A
公开(公告)日：2000-07-15
申请号：KR1019980061385
申请日：1998-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/76
摘要： PURPOSE: A method for fabricating a shallow trench isolation film of a semiconductor device is provided to improve the reliance of the shallow trench isolation film by removing an oxide layer remaining in a broad active area and by preventing an over-etching of a narrow active area. CONSTITUTION: Broad and narrow active areas(10,30) and field areas are defined. An etching resist layer pattern in which the filed areas are opened is formed on a semiconductor substrate(21). By using the etching resist layer pattern, the semiconductor substrate(21) is etched so that broad and narrow trenches are formed. Then, an oxide layer(22) for filling the trenches is formed on the structure. The oxide layer(22) on the broad active areas(10) is partially removed. By polishing the oxide layer(22), the oxide layer(21) remains in the trenches and then the etching resist layer is removed.
摘要翻译：目的：提供一种用于制造半导体器件的浅沟槽隔离膜的方法，以通过去除残留在宽有效区域中的氧化物层并通过防止窄的有源区域的过度蚀刻来改善浅沟槽隔离膜的依赖性。规定：确定广泛而狭窄的活动区域（10,30）和野外区域。在半导体衬底（21）上形成其中开有场区的蚀刻抗蚀剂层图案。通过使用抗蚀剂层图案，蚀刻半导体衬底（21），从而形成宽而窄的沟槽。然后，在该结构上形成用于填充沟槽的氧化物层（22）。部分去除广泛的有源区域（10）上的氧化物层（22）。通过研磨氧化物层（22），氧化物层（21）保留在沟槽中，然后除去抗蚀剂层。

49. 发明公开

KR1020000044880A 반도체 소자의 쉘로우 트랜치 소자분리막 형성방법 无效
标题翻译：用于形成半导体器件的浅层分离的方法
公开(公告)号：KR1020000044880A
公开(公告)日：2000-07-15
申请号：KR1019980061383
申请日：1998-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/76
摘要： PURPOSE: A method for forming a shallow trench isolation of a semiconductor device is provided which can suppress the over-polishing phenomenon or the phenomenon that a trench-burying oxide is remained during a planarization process. CONSTITUTION: A method for forming a shallow trench isolation suppresses the over-polishing and the remaining of a trench-burying oxide(25) during a planarization process, by performing the planarization process after removing the trench-burying oxide on a top of a wide active region using a reverse mask(26). The method includes the steps of: defining a number of wide and narrow active regions and field regions, and forming an etching resistant pattern(22,23) on a semiconductor substrate(21); forming a number of wide and narrow trenches by etching the semiconductor substrate with an etching process using the etching resistant pattern; forming the trench-burying oxide on a top of the whole structure including the trenches; forming a trench-burying oxide pattern on the active region, by removing a part of the trench-burying oxide on the wide active region; and removing the etching resistant pattern, after remaining the trench-burying oxide in the trench by polishing the trench-burying oxide.
摘要翻译：目的：提供一种用于形成半导体器件的浅沟槽隔离的方法，其可以抑制在抛光过程中过度抛光现象或保留沟槽氧化物的现象。构成：用于形成浅沟槽隔离的方法在平坦化处理期间通过在去除宽的顶部上的沟槽埋入氧化物之后执行平坦化处理来抑制过度抛光和剩余的沟槽埋入氧化物（25）有源区域使用反向掩模（26）。该方法包括以下步骤：定义多个宽而窄的有源区和场区，并在半导体衬底（21）上形成抗蚀图案（22,23）; 通过使用耐蚀刻图案的蚀刻工艺蚀刻半导体衬底来形成多个窄沟槽; 在包括沟槽的整个结构的顶部上形成沟槽埋置氧化物; 通过在宽有效区域上去除一部分沟槽埋入氧化物，在有源区上形成沟槽埋置氧化物图形; 并且通过抛光沟槽埋入氧化物而在沟槽中保留沟槽埋入氧化物之后去除抗蚀刻图案。

50. 发明公开

KR1020000044879A 반도체 소자의 소자분리막 형성 방법 无效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：KR1020000044879A
公开(公告)日：2000-07-15
申请号：KR1019980061382
申请日：1998-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 여인석
IPC分类号： H01L21/76
摘要： PURPOSE: A method for forming an isolation film of a semiconductor device is provided which suppresses the thinning phenomenon of an isolation film and improves the characteristics of the isolation film. CONSTITUTION: A method for forming an isolation(16) suppresses the thinning phenomenon by controlling the growth rate of the isolation film on a region where the width of the isolation film is narrow to be faster than on a region where the width of the isolation film is wide. The method also improves the GOI(gate oxide integrity) characteristics of an active region and the junction leakage current characteristics, without an additional process to suppress bird's beak generated on the active region because the isolation film can be formed sufficiently thick. Therefore, the method improves the yield and the refresh characteristics of the device.
摘要翻译：目的：提供一种形成半导体器件的隔离膜的方法，其抑制隔离膜的变薄现象并提高隔离膜的特性。构成：形成隔离（16）的方法通过控制隔离膜的宽度窄的区域上的隔离膜的生长速度比隔离膜的宽度的区域更快地抑制薄化现象很宽该方法还提高了有源区的GOI（栅极氧化物完整性）特性和结漏电流特性，而不需要另外的方法来抑制由于隔离膜形成得足够厚而在有源区上产生的鸟嘴。因此，该方法提高了装置的产量和刷新特性。

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