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41. 发明公开

KR1020130110599A 트랜지스터, 반도체 소자 및 이를 포함하는 반도체 모듈 审中-实审
标题翻译：晶体管，半导体器件和包括其的半导体器件
公开(公告)号：KR1020130110599A
公开(公告)日：2013-10-10
申请号：KR1020120032685
申请日：2012-03-29
申请人： 삼성전자주식회사
发明人： 허기재 , 야마다사토루 , 임준희 , 장성호
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L27/04 , H01L29/41766 , H01L29/4236 , H01L29/78 , H01L29/785 , H01L29/66621 , H01L29/66795
摘要： PURPOSE: A transistor, a semiconductor device, and a semiconductor module including the same improve the resistance characteristics of wiring including a gate electrode of a transistor by composing the gate electrode with two or more conductive materials having different work functions. CONSTITUTION: A field region (7) limits an active region (9) by being formed within a substrate (1). A first source/drain region (60) and a second source/drain region (87) are separated from each other within the active region. A gate trench (18) includes a first part (18a) crossing the active region and a second part (18b) in the field region. A gate structure (GS) is formed within the gate trench. The gate structure includes a gate electrode (36), a gate capping pattern (45), a gate dielectric (24), and a metal-containing material film (39). The metal-containing material film is formed between the gate capping pattern and the active region.
摘要翻译：目的：晶体管，半导体器件和包括该晶体管的半导体模块通过组合栅电极与具有不同功函的两种或多种导电材料来提高包括晶体管的栅电极的布线的电阻特性。构成：场区域（7）通过形成在衬底（1）内而限制有源区域（9）。第一源极/漏极区域（60）和第二源极/漏极区域（87）在有源区域内彼此分离。栅极沟槽（18）包括与激活区域交叉的第一部分（18a）和场区域中的第二部分（18b）。栅极结构（GS）形成在栅极沟槽内。栅极结构包括栅极电极（36），栅极覆盖图案（45），栅极电介质（24）和含金属的材料膜（39）。含金属材料膜形成在栅极封盖图案和有源区域之间。

42. 发明授权

KR100843711B1 리세스 채널 영역을 갖는 트랜지스터를 채택하는반도체소자 및 그 제조방법 有权
标题翻译：使用带有通道的晶体管的半导体器件及其制造方法
公开(公告)号：KR100843711B1
公开(公告)日：2008-07-04
申请号：KR1020070018442
申请日：2007-02-23
申请人： 삼성전자주식회사
发明人： 장성호 , 최용진 , 강민성 , 이광우
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L27/10814 , H01L27/10876 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： A semiconductor device including a transistor having a recess channel region and a manufacturing method thereof are provided to enhance reliability by forming smooth corners between trench regions having different widths. A trench structure(133) includes upper trench regions(115) having different widths, buffer trench regions(125), and lower trench regions(130). The upper trench regions are sequentially arranged from a surface of an active region(105a) of a semiconductor substrate(100) to a lower direction. A gate electrode(145) is formed in the trench structure. A gate dielectric layer(140) is inserted between the gate electrode and the trench structure. In the trench structure, the widths of the trench regions are getting increased from the surface of the active region to the lower direction.
摘要翻译：提供一种包括具有凹槽通道区域的晶体管及其制造方法的半导体器件，以通过在具有不同宽度的沟槽区域之间形成平滑的角来提高可靠性。沟槽结构（133）包括具有不同宽度的上沟槽区域（115），缓冲沟槽区域（125）和下沟槽区域（130）。上沟槽区域从半导体衬底（100）的有源区（105a）的表面向下方顺序排列。在沟槽结构中形成栅电极（145）。栅电介质层（140）插入在栅电极和沟槽结构之间。在沟槽结构中，沟槽区域的宽度从有源区域的表面增加到较低的方向。

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