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31. 发明公开

KR1020110075331A 반도체 장치 无效
标题翻译： SEMICONDUCTOR APPARATUS
公开(公告)号：KR1020110075331A
公开(公告)日：2011-07-06
申请号：KR1020090131753
申请日：2009-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 김정욱
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1051 , G11C2207/2272
摘要： PURPOSE: A semiconductor apparatus is provided to transmit and receives data at the same edge of a clock signal and an output clock signal by adjusting a delay vale to allow a receiver to accurately data. CONSTITUTION: In a semiconductor apparatus, first and second semiconductor chips(30,40) exchange a signal through a transmission channel. The first semiconductor chip comprises a clock generator(310) and a data receiver(320) The clock generator generates a clock signal. The data receiver receives a data signal. The data signal is transmitted through the transmission channel. A second semiconductor chip comprises a variable delayer(420), a phase shifter(430), a selecting unit(440), a data transmitter(460) and a clock delay control part(450).
摘要翻译：目的：提供一种半导体装置，通过调整延迟值来允许接收机准确地进行数据，在时钟信号和输出时钟信号的相同边缘发送和接收数据。构成：在半导体装置中，第一和第二半导体芯片（30,40）通过传输通道交换信号。第一半导体芯片包括时钟发生器（310）和数据接收器（320）。时钟发生器产生时钟信号。数据接收器接收数据信号。数据信号通过传输通道传输。第二半导体芯片包括可变延迟器（420），移相器（430），选择单元（440），数据发送器（460）和时钟延迟控制部分（450）。

32. 发明公开

KR1020110060740A 반도체 메모리의 동작 타이밍 제어 장치 및 그 방법 失效
标题翻译：用于控制半导体存储器的操作时序的装置和方法
公开(公告)号：KR1020110060740A
公开(公告)日：2011-06-08
申请号：KR1020090117422
申请日：2009-11-30
申请人： 에스케이하이닉스 주식회사
发明人： 윤현수 , 이종천
IPC分类号： G11C11/4076 , G11C11/407
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/2272
摘要： PURPOSE: An apparatus and a method for controlling the operation timing of semiconductor memory are provided to control the termination operation timing of a corresponding command using control information for a shift resistor. CONSTITUTION: A control information generating unit generates control information. The control information is based on data path delay information and latency information. A register shifts corresponding command according to the control information. A DLL delay unit(140) delays a shifted command through a delay locked loop. A control information generating unit comprises a data route delay part(110) and a latency processing unit(120). The data route delay part calculates data path delay information. The latency processing unit offers the latency information.
摘要翻译：目的：提供用于控制半导体存储器的操作定时的装置和方法，以使用用于移位电阻器的控制信息来控制对应命令的终止操作定时。构成：控制信息生成部生成控制信息。控制信息基于数据路径延迟信息和延迟信息。寄存器根据控制信息移动相应的命令。 DLL延迟单元（140）通过延迟锁定环延迟移位的命令。控制信息生成单元包括数据路径延迟部（110）和等待时间处理部（120）。数据路径延迟部分计算数据路径延迟信息。延迟处理单元提供延迟信息。

33. 发明公开

KR1020110040538A 레이턴시 회로 및 이를 포함하는 반도체 장치 无效
标题翻译：包括其中的电路和半导体器件
公开(公告)号：KR1020110040538A
公开(公告)日：2011-04-20
申请号：KR1020090097851
申请日：2009-10-14
申请人： 삼성전자주식회사
发明人： 전인우 , 정병훈 , 김민수
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C7/227 , G11C8/18 , G11C2207/2272
摘要： PURPOSE: A latency circuit and a semiconductor device including the same are provided to stably generate a latency signal in regardless of the operation of a high frequency and PVT variation. CONSTITUTION: A latency control block(110) delays a delayed synchronous signal. The latency control block generates a plurality of first control clocks. The latency control block generates a second control clock. The second control clock has a certain margin of a read command. An inside read command generator(120) samples the second control clock. The inside read command generator generates an inside read command. A latency signal generating unit(130) generates a latency signal.
摘要翻译：目的：提供延迟电路和包括该延迟电路的半导体器件，以稳定地生成等待时间信号，而与高频和PVT变化的操作无关。构成：等待时间控制块（110）延迟延迟的同步信号。等待时间控制块产生多个第一控制时钟。等待时间控制块产生第二控制时钟。第二个控制时钟具有读取命令的一定余量。内部读命令生成器（120）对第二控制时钟进行采样。内部读取命令生成器生成内部读取命令。延迟信号生成单元（130）生成等待时间信号。

34. 发明公开

KR1020100131141A 반도체 메모리장치의 센스앰프 오버드라이브회로 无效
标题翻译：用于半导体存储器件的感测放大器放大电路
公开(公告)号：KR1020100131141A
公开(公告)日：2010-12-15
申请号：KR1020090049882
申请日：2009-06-05
申请人： 에스케이하이닉스 주식회사
发明人： 이강열
IPC分类号： G11C7/06 , G11C7/08 , G11C7/10
CPC分类号： G11C7/08 , G11C2207/065 , G11C2207/2272
摘要： PURPOSE: The sense amplifier overdrive circuit of a semiconductor memory device is provided to modify the write recovery time of the device by re-implementing a sense amplifying overdrive operation in the data recording operation of a memory cell. CONSTITUTION: A first signal generating part(100) includes a p-type metal oxide semiconductor transistor(101), an n-type metal oxide semiconductor transistor(103), an inverter(104) and a NAND gate(105). A fourth signal generating part(360) includes an inverter(361), a delaying part, and a NAND gate(363). The inverter generates a pulse in the falling edge of a column enable signal. The delaying part delays the output of the inverter. The NAND gate calculates the outputs of the delaying part and the inverter.
摘要翻译：目的：提供半导体存储器件的读出放大器过驱动电路，通过在存储器单元的数据记录操作中重新实现读出放大过驱动操作来修改器件的写恢复时间。构成：第一信号产生部分（100）包括p型金属氧化物半导体晶体管（101），n型金属氧化物半导体晶体管（103），反相器（104）和与非门（105）。第四信号产生部分（360）包括反相器（361），延迟部分和与非门（363）。逆变器在列使能信号的下降沿产生脉冲。延迟部分延迟变频器的输出。 NAND门计算延迟部分和逆变器的输出。

35. 发明公开

KR1020100125917A 독출 레이턴시 검출 기능을 갖는 메모리 컨트롤러, 및 이를 구비한 메모리 시스템 无效
标题翻译：具有读取功能的存储器控制器检测功能和存储器控制器的存储器系统
公开(公告)号：KR1020100125917A
公开(公告)日：2010-12-01
申请号：KR1020090044879
申请日：2009-05-22
申请人： 삼성전자주식회사
发明人： 최훈대 , 장영찬
IPC分类号： G11C11/409 , G11C7/22
CPC分类号： G11C29/50 , G11C29/50012 , G11C29/56012 , G11C2207/2272
摘要： PURPOSE: A memory controller including a rear latency detecting function and a method system including the same are provided to accurately sample data using a clock signal by setting a valid window with respect to data. CONSTITUTION: A semiconductor memory device(1500) communicates with a memory controller(1100) through a first channel(CH1) and a second channel(CH2). A data strobe signal(DQS) passes through the first channel. DATA(DQ) passes through the second channel. A read latency detecting circuit generates a first signal based on a system clock signal. A clock domain synchronizing circuit generates a delay selection signal and a hold signal based on the system clock signal and a second signal.
摘要翻译：目的：提供包括后延迟检测功能的存储器控制器和包括其的方法系统，以通过设置关于数据的有效窗口来使用时钟信号来精确地采样数据。构成：半导体存储器件（1500）通过第一通道（CH1）和第二通道（CH2）与存储器控制器（1100）通信。数据选通信号（DQS）通过第一通道。 DATA（DQ）通过第二个通道。读延迟检测电路基于系统时钟信号产生第一信号。时钟域同步电路基于系统时钟信号和第二信号产生延迟选择信号和保持信号。

36. 发明公开

KR1020100099892A 저 주파수에서 과도한 듀티 싸이클 보정을 방지할 수 듀티 싸이클 보정기 无效
标题翻译：能够在低频下预防过度的周期循环校正的占空比校正器
公开(公告)号：KR1020100099892A
公开(公告)日：2010-09-15
申请号：KR1020090018459
申请日：2009-03-04
申请人： 삼성전자주식회사
发明人： 신원화
IPC分类号： G11C11/407 , G11C8/00
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272 , H03K5/1565
摘要： PURPOSE: A duty cycle corrector capable of preventing excessive duty cycle correction in low frequency is provided to prevent the excessive increase of variation amount of common mode by disabling a common mode control circuit. CONSTITUTION: A duty cycle correction amplifier(31) amplifies the complementation input clock signal of the input clock signal and input clock signal. A low frequency detector(35) detects the frequency of the input clock signal lower than the predetermined frequency. A control circuit(37) receives the complementation duty control signal of the duty control signal and the duty control signal.
摘要翻译：目的：提供能够防止低频率的过载占空比校正的占空比校正器，以通过禁用共模控制电路来防止共模变化量的过度增加。构成：占空比校正放大器（31）放大输入时钟信号和输入时钟信号的互补输入时钟信号。低频检测器（35）检测低于预定频率的输入时钟信号的频率。控制电路（37）接收占空比控制信号和占空比控制信号的互补占空比控制信号。

37. 发明公开

KR1020100083626A 반도체 메모리 장치 无效
标题翻译：半导体存储器件
公开(公告)号：KR1020100083626A
公开(公告)日：2010-07-22
申请号：KR1020090003101
申请日：2009-01-14
申请人： 삼성전자주식회사
发明人： 이창용 , 한공흠
IPC分类号： G11C5/02 , G11C5/06 , G11C5/14
CPC分类号： G11C7/22 , G11C7/18 , G11C8/12 , G11C2207/2272
摘要： PURPOSE: A semiconductor memory device is provided to obtain contest AC characteristics since constant power is consumed in memory banks which are active. CONSTITUTION: A semiconductor memory device(10) comprises a plurality of banks(111-118,121-128,131-138,141-148), a peripheral circuit exchanging data with the plural banks, and a data line connecting the banks and the peripheral circuit. The peripheral circuit comprises an internal power supply circuits which supply power to the banks through a mesh structure line. The sum of distance between the activated banks and the internal power supply circuit is constant.
摘要翻译：目的：提供半导体存储器件以获得竞争AC特性，因为在有效的存储体中消耗了恒定功率。构成：半导体存储器件（10）包括多个存储体（111-118,121-128,131-138,141-148），与多个存储体交换数据的外围电路以及连接存储体和外围电路的数据线。外围电路包括通过网状结构线向堤提供电力的内部电源电路。激活的组和内部电源电路之间的距离之和是恒定的。

38. 发明公开

KR20100078987A Semiconductor device 无效
标题翻译：半导体器件
公开(公告)号：KR20100078987A
公开(公告)日：2010-07-08
申请号：KR20080137382
申请日：2008-12-30
申请人： HYNIX SEMICONDUCTOR INC
发明人： KIM KYUNG HOON
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： H03L7/0814 , G11C7/1045 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： PURPOSE: A semiconductor device is provided to generate a latency signal by measuring the degree of delay of a delay locked loop. CONSTITUTION: An internal clock signal generation unit generates a delay controlling signal. The internal clock signal generation unit delays reference clock signal to generate the internal clock signal. The internal clock signal generation unit generates a feedback clock signal. A latency generation unit synchronizes a read command signal with the internal clock signal. The latency generation unit generates a latency signal. The input control unit controls the activation of the reference clock signal.
摘要翻译：目的：提供半导体器件以通过测量延迟锁定环路的延迟程度来产生等待时间信号。构成：内部时钟信号生成部生成延迟控制信号。内部时钟信号发生单元延迟参考时钟信号以产生内部时钟信号。内部时钟信号生成单元生成反馈时钟信号。延迟生成单元使读取命令信号与内部时钟信号同步。延迟生成单元生成等待时间信号。输入控制单元控制参考时钟信号的激活。

39. 发明公开

KR1020100073620A 반도체 메모리 장치의 동기 회로 无效
标题翻译：半导体存储器同步电路
公开(公告)号：KR1020100073620A
公开(公告)日：2010-07-01
申请号：KR1020080132336
申请日：2008-12-23
申请人： 에스케이하이닉스 주식회사
发明人： 김영주
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1072 , G11C2207/2272
摘要： PURPOSE: A synchronous circuit of a semiconductor memory device is provided to improve operation reliability by generating output data by synchronizing the rising edge of a clock with the center of input data. CONSTITUTION: A rising edge timing control unit(100) receives a clock and generates a control clock. The control clock is transited to a high state in a faster or slower timing than the rising edge. A data clock synchronization unit(10) receives input data in the rising edge of the control clock and outputs the input data.
摘要翻译：目的：提供半导体存储器件的同步电路，通过使时钟的上升沿与输入数据的中心同步来产生输出数据来提高操作的可靠性。构成：上升沿定时控制单元（100）接收时钟并产生控制时钟。控制时钟以比上升沿更快或更慢的时序转换到高电平状态。数据时钟同步单元（10）在控制时钟的上升沿接收输入数据并输出输入数据。

40. 发明授权

KR100948077B1 Semiconductor memory device and method for driving the same 无效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：KR100948077B1
公开(公告)日：2010-03-16
申请号：KR20080090436
申请日：2008-09-12
申请人： HYNIX SEMICONDUCTOR INC
发明人： HONG NAM PYO
IPC分类号： G11C8/00 , G11C7/22
CPC分类号： G11C7/222 , G11C2207/2272 , H03K5/1565 , H03L7/0814 , H03L7/085
摘要： PURPOSE: A semiconductor memory device and a driving method thereof are provided to improve a yield by improving the reliability and operating stability of the semiconductor memory device including a delay locked loop. CONSTITUTION: A delay locked loop comprises a plurality of synchronization operation unit synchronized with an external clock. The delay locked loop comprises at least one asynchronization operation unit asynchronized with the external clock. A control signal generating unit successively generates a plurality of control signals for controlling the synchronization operation units every delay shift update period. The control signal generating unit controls the delay locked loop by adjusting the activation time interval of the control signals according to the frequency of the external clock. The control signal generating unit comprises the 22 number of D flip-flops(DFF101~DFF122). A frequency detector(300) generates a control signal by operating the D flip-flop.
摘要翻译：目的：提供半导体存储器件及其驱动方法，通过提高包括延迟锁定环路的半导体存储器件的可靠性和操作稳定性来提高产量。构成：延迟锁定环包括与外部时钟同步的多个同步操作单元。延迟锁定环包括与外部时钟不同步的至少一个异步操作单元。控制信号生成单元在每个延迟移位更新期间依次生成用于控制同步运算单元的多个控制信号。控制信号发生单元通过根据外部时钟的频率调节控制信号的激活时间间隔来控制延迟锁定环路。控制信号生成单元包括22个D触发器（DFF101〜DFF122）。频率检测器（300）通过操作D触发器来产生控制信号。

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