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21. 发明公开

KR1020140024669A 반도체메모리장치 无效
标题翻译：半导体存储器件
公开(公告)号：KR1020140024669A
公开(公告)日：2014-03-03
申请号：KR1020120090938
申请日：2012-08-20
申请人： 에스케이하이닉스 주식회사
发明人： 박민수
IPC分类号： G11C8/14 , G11C8/08 , G11C29/00
CPC分类号： G11C29/04 , G11C7/06 , G11C8/08 , G11C11/4085 , G11C11/4091 , G11C11/4099 , G11C29/783
摘要： A semiconductor device comprises: a first cell block which contains memory cells connected to a first word line activated in response to a low address; a second cell block which contains memory cells connected to a second word line activated in response to the low address; and a dummy cell block which contains memory cells connected to a third word line activated in response to the low address. The first and the second cell blocks share a first sense amplifier, and the second cell block and the dummy cell block share a second sense amplifier. The first cell block is located near an edge in which the low address is entered, and the dummy cell block is located near an edge opposite to the edge where the low address is entered. [Reference numerals] (12) First sense amplifier; (14) Second sense amplifier; (16) First word line driver; (17) Second word line driver; (18) Third word line driver; (19) Repair unit
摘要翻译：半导体器件包括：第一单元块，其包含连接到响应于低地址而被激活的第一字线的存储器单元; 第二单元块，其包含连接到响应于低地址而被激活的第二字线的存储器单元; 以及包含连接到响应于低地址而被激活的第三字线的存储单元的虚拟单元块。第一和第二单元块共享第一读出放大器，并且第二单元块和虚设单元块共享第二读出放大器。第一个单元块位于其中输入低地址的边缘附近，并且虚设单元块位于与输入低地址的边缘相对的边缘附近。（附图标记）（12）第一读出放大器; （14）第二感测放大器; （16）第一个字线驱动程序; （17）第二字线驱动器; （18）第三字线驱动器; （19）维修单位

22. 发明公开

KR1020130078455A 메모리 특성 정보를 저장하는 반도체 메모리 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 반도체 메모리 장치의 동작방법 无效
标题翻译：半导体存储器件存储器存储器特征信息，存储器模块和存储器系统及其操作方法
公开(公告)号：KR1020130078455A
公开(公告)日：2013-07-10
申请号：KR1020110147415
申请日：2011-12-30
申请人： 삼성전자주식회사
发明人： 유학수 , 최주선 , 황홍선
IPC分类号： G11C11/4063 , G11C11/408 , G11C7/10
CPC分类号： G11C11/4063 , G11C11/406 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C29/783 , G11C2211/4061
摘要： PURPOSE: A semiconductor memory device storing memory characteristic information, a memory module including the same, a memory system, and an operation method of the semiconductor memory device are provided to reduce the impact of a weak cell or a weak page on a memory operation by managing the memory operation using the stored characteristic information. CONSTITUTION: A cell array includes multiple regions accessed by a first address. A non-volatile array (1110) stores group information in which each region is included for the multiple regions classified into two groups according to memory characteristics. The group information is successively stored in the non-volatile array according to a first address value of the regions.
摘要翻译：目的：提供一种存储存储特性信息的半导体存储器件，包括该半导体存储器件的存储器模块，存储器系统和操作方法，以减少弱电池或弱电压对存储器操作的影响使用存储的特征信息来管理存储器操作。构成：单元阵列包括由第一个地址访问的多个区域。根据存储特性，非易失性阵列（1110）存储组信息，其中包括分为两组的多个区域的每个区域。组信息根据区域的第一地址值被连续地存储在非易失性阵列中。

23. 发明授权

KR100857448B1 반도체 메모리 장치의 리셋펄스 생성회로 失效
标题翻译：用于产生半导体存储器装置的复位脉冲的电路
公开(公告)号：KR100857448B1
公开(公告)日：2008-09-10
申请号：KR1020070056961
申请日：2007-06-11
申请人： 에스케이하이닉스 주식회사
发明人： 김경태
IPC分类号： G11C11/4072 , G11C11/401 , G11C11/406 , G11C11/4076
CPC分类号： G11C11/4072 , G11C7/20 , G11C11/406 , G11C29/04 , G11C29/783
摘要： A circuit for generating a reset pulse of a semiconductor memory apparatus is provided to find a defective address during a specific test with inputted refresh. A refresh reset pulse generation part(100) generates a refresh reset signal in response to a row address signal. A reset pulse generation part(200) generates a reset pulse signal initializing a counter in response to the refresh reset signal, a test signal or a power up signal. The refresh reset pulse generation part generates the refresh reset signal, when a normal refresh signal and a redundancy refresh signal are disabled.
摘要翻译：提供用于产生半导体存储装置的复位脉冲的电路，用于在具有输入刷新的特定测试期间找到缺陷地址。刷新复位脉冲产生部分（100）响应于行地址信号产生刷新复位信号。复位脉冲产生部分（200）响应于刷新复位信号，测试信号或上电信号产生初始化计数器的复位脉冲信号。当正常刷新信号和冗余刷新信号被禁用时，刷新复位脉冲产生部分产生刷新复位信号。

24. 发明授权

KR100833592B1 반도체 메모리 장치 및 반도체 메모리의 리프레시 방법 失效
标题翻译：半导体存储器件和半导体存储器刷新方法
公开(公告)号：KR100833592B1
公开(公告)日：2008-05-30
申请号：KR1020060135724
申请日：2006-12-27
申请人： 에스케이하이닉스 주식회사
发明人： 문형욱
IPC分类号： G11C11/401 , G11C29/00
CPC分类号： G11C11/406 , G11C11/4072 , G11C11/4085 , G11C29/12 , G11C29/783
摘要： A semiconductor memory device and a refresh method of a semiconductor memory are provided to reduce test time by testing failures of a normal cell and a redundant cell at the same time, by refreshing a normal word line and a redundancy word line sequentially. A refresh counter outputs a refresh address and a first control signal by a refresh signal. A first selection signal generation part(120) outputs a first selection signal controlling to select a refresh word line in correspondence to the enable of the refresh signal. A second selection signal generation part(140) outputs a second selection signal controlling to select an active word line in correspondence to the disable of the refresh signal. An output part(160) outputs a third selection signal enabling one of a normal word line and a redundancy word line by the first and the second selection signal.
摘要翻译：提供半导体存储器件和半导体存储器的刷新方法，通过依次刷新正常字线和冗余字线来同时通过测试正常单元和冗余单元的故障来减少测试时间。刷新计数器通过刷新信号输出刷新地址和第一控制信号。第一选择信号生成部分（120）输出与刷新信号的使能对应的控制选择刷新字线的第一选择信号。第二选择信号生成部（140）输出控制与选择有效字线对应的刷新信号的禁止的第二选择信号。输出部分（160）通过第一选择信号和第二选择信号输出通常的字线和冗余字线之一的第三选择信号。

25. 发明公开

KR1020070069878A 반도체 장치 有权
标题翻译：半导体器件
公开(公告)号：KR1020070069878A
公开(公告)日：2007-07-03
申请号：KR1020050132468
申请日：2005-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 이종원
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C11/406 , G11C8/14 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C11/4085 , G11C29/783 , G11C2211/4061 , G11C8/08
摘要： A semiconductor device is provided to reduce the size of the semiconductor device due to decrease in the size of a redundant word line by allowing various memory banks to share the same redundant word line. A semiconductor device includes plural memory banks. An address controller(200) receives a normal address and a refresh address, and selectively outputs the refresh address at a refresh mode. A fuse unit(400) receives the refresh address, determines whether the refresh address corresponds to a repaired word line, and outputs a redundant word line enable signal and a first control signal. A first signal generator(500) outputs a second control signal for defining multiple word line refresh periods in response to a block selection address and the first control signal. A refresh address generator(600) generates the refresh address in response to the second control signal. A row controller(700) receives the refresh address, the second control signal, and the redundant word line enable signal and controls a refresh process on a memory core. During a self refresh mode, a multiple word line refresh process is performed when the refresh address corresponds to the normal word line, and a single word line refresh process is performed when the refresh address corresponds to the repaired word line.
摘要翻译：提供一种半导体器件，通过允许各种存储体共享相同的冗余字线，由于冗余字线的尺寸的减小而减小了半导体器件的尺寸。半导体器件包括多个存储体。地址控制器（200）接收正常地址和刷新地址，并且在刷新模式下有选择地输出刷新地址。熔丝单元（400）接收刷新地址，确定刷新地址是否对应于修复后的字线，并输出冗余字线使能信号和第一控制信号。响应于块选择地址和第一控制信号，第一信号发生器（500）输出用于定义多个字线刷新周期的第二控制信号。刷新地址发生器（600）响应于第二控制信号产生刷新地址。行控制器（700）接收刷新地址，第二控制信号和冗余字线使能信号，并控制对存储器核心的刷新处理。在自刷新模式期间，当刷新地址对应于正常字线时执行多字线刷新处理，并且当刷新地址对应于修复后的字线时，执行单个字线刷新处理。

26. 发明授权

KR100571329B1 반도체 메모리 有权
标题翻译：半导体内存
公开(公告)号：KR100571329B1
公开(公告)日：2006-04-17
申请号：KR1020040114026
申请日：2004-12-28
申请人： 후지쯔 가부시끼가이샤
发明人： 오쿠야마요시아키 , 모리가오루
IPC分类号： G11C29/00 , G11C11/4193 , G11C11/4197 , G11C8/06
CPC分类号： G11C11/406 , G11C11/40603 , G11C29/783
摘要： 본 발명은 반도체 메모리의 액세스 시간을 단축하는 것을 목적으로 한다.
재정 회로(22)는 내부 액세스 요구(IREFZ) 및 외부 액세스 요구(RDZ, WRZ)가 경합할 때에 어느 쪽을 우선시킬 것인지를 판정한다. 용장 판정 회로(28)는 내부 액세스 요구(IREFZ) 및 외부 액세스 요구(RDZ, WRZ)에 각각 대응하여 통상 메모리 셀 또는 용장 메모리 셀의 어느 것을 액세스할 것인지를 판정한다(용장 판정). 용장 판정 회로(28)는 재정 회로(22)가 내부 액세스 요구(IREFZ)를 우선할 때, 외부 액세스 요구(RDZ, WRZ)에 대응하는 용장 판정을 내부 액세스 동작중에 실행한다. 유지 회로(32)는 메모리 코어(34)의 오동작을 방지하기 위해서 용장 판정 결과를 유지하여, 외부 액세스 요구(RDZ, WRZ)에 따르는 용장 판정 결과가 내부 액세스 동작을 실행하고 있는 메모리 코어(34)에 전달되는 것을 방지한다.
摘要翻译：本发明的一个目的是缩短半导体存储器的存取时间。

27. 发明公开

KR1020030047029A 반도체 메모리 소자의 리프레쉬장치 및 그것의 리프레쉬방법 失效
标题翻译：半导体存储器件的刷新器件及其刷新方法
公开(公告)号：KR1020030047029A
公开(公告)日：2003-06-18
申请号：KR1020010077404
申请日：2001-12-07
申请人： 에스케이하이닉스 주식회사
发明人： 윤석철 , 이재진 , 강상희 , 김철호
IPC分类号： G11C11/401
CPC分类号： G11C29/783 , G11C11/406 , G11C11/4085 , G11C11/4087 , G11C29/24 , G11C2029/1202 , G11C2029/1802
摘要： PURPOSE: A refresh device of a semiconductor memory device and a refreshing method thereof are provided to refresh simultaneously a normal cell and a redundant cell by driving simultaneously a redundant main word line and a normal main word line at one test mode. CONSTITUTION: A refresh device includes a redundant cell refresh signal generation portion(150), a word line enable signal generation portion(160), and a plurality of word line drivers(190,200). The redundant cell refresh signal generation portion generates a redundant cell refresh signal in order to refresh a redundant cell according to a refresh request at a test mode. The word line enable signal generation portion generates a normal main word line enable signal and a redundant main word line enable signal in response to the redundant cell refresh signal at a redundant cell test mode. The word line drivers are used for refreshing simultaneously a normal cell and a redundant cell in response to the redundant cell refresh signal, the normal main word line enable signal, the redundant main word line enable signal, and the plural row address signals at the redundant cell test mode.
摘要翻译：目的：提供一种半导体存储器件的刷新装置及其刷新方法，用于在一个测试模式下同时驱动冗余主字线和正常主字线同时刷新正常单元和冗余单元。构成：刷新装置包括冗余单元刷新信号生成部分（150），字线使能信号生成部分（160）和多个字线驱动器（190,200）。冗余单元刷新信号生成部生成冗余单元刷新信号，以便在测试模式下根据刷新请求刷新冗余单元。字线使能信号生成部分响应于冗余单元测试模式下的冗余单元刷新信号，产生正常主字线使能信号和冗余主字线使能信号。字线驱动器用于响应于冗余单元刷新信号，正常主字线使能信号，冗余主字线使能信号和多余行冗余单元冗余单元刷新冗余单元和冗余单元电池测试模式。

28. 发明公开

KR20180061445A 메모리 장치 审中-公开
公开(公告)号：KR20180061445A
公开(公告)日：2018-06-08
申请号：KR20160159171
申请日：2016-11-28
IPC分类号： G11C29/42 , G06F11/10 , G11C11/406 , G11C29/00
CPC分类号： G11C29/783 , G11C29/42
摘要： 메모리장치는다수의메모리셀; 상기다수의메모리셀 중데이터보유시간이기준시간보다짧은하나이상의위크셀의위크어드레스및 상기하나이상의위크셀에대응하는패리티정보를저장하는위크셀 정보저장부; 상기패리티정보를이용하여상기하나이상의위크셀의에러비트를검출하고정정하는 ECC(Error Correction Code) 회로; 및상기다수의메모리셀이상기기준시간이상의주기로리프레시되도록제어하는리프레시제어부를포함할수 있다.

29. 发明公开

KR1020170098647A 리프레쉬방법 및 이를 이용한 반도체장치 审中-实审
标题翻译：刷新方法及使用其的半导体器件
公开(公告)号：KR1020170098647A
公开(公告)日：2017-08-30
申请号：KR1020160020840
申请日：2016-02-22
申请人： 에스케이하이닉스 주식회사
发明人： 김육희
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/406 , G11C11/4085 , G11C11/4087 , G11C17/16 , G11C17/18 , G11C29/78 , G11C29/781 , G11C29/783 , G11C29/808 , G11C29/81
摘要： 반도체장치는커맨드에응답하여생성되는어드레스와불량어드레스를비교하여상기커맨드입력시점으로부터기 설정된구간동안순차적으로인에이블되는노멀워드라신호및 리던던시워드라인신호를생성하는리프레쉬제어회로및 상기노멀워드라인신호가인에이블되는경우상기어드레스에응답하여불량이발생한불량워드라인이비활성화되고, 상기리던던시워드라인신호가인에이블되는경우상기불량워드라인이대체되는리던던시워드라인이활성화되는메모리회로를포함하는반도체장치를포함한다.
摘要翻译：该半导体器件被刷新，用于比较地址和不良地址来响应于所述命令来产生生成部依次使正常字拉信号和用于从所述指令输入的设定时段一个冗余字线信号定时控制电路和正常字线并且当响应于地址使能信号时激活冗余字线信号被使能时替换缺陷字线的冗余字线被激活，它包括。

30. 发明公开

KR1020160078396A 집적 회로 결함 검출 및 복구 审中-实审
标题翻译：集成电路缺陷检测和维修
公开(公告)号：KR1020160078396A
公开(公告)日：2016-07-04
申请号：KR1020167013581
申请日：2014-12-22
申请人： 인텔 코포레이션
发明人： 퀘르바흐,브루스 , 쇤보른,테어도르제트. , 짐머만,데이비드제이. , 엘리스,데이비드지. , 햄프슨,크리스토퍼더블유. , 완,이파르 , 장,율란 , 말레라,라마크리슈나 , 루이,윌리엄케이.
IPC分类号： G11C29/10 , G06F11/263 , G06F11/27 , G11C29/36 , G11C29/44
CPC分类号： G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
摘要： 본설명에따르면, 디바이스는, 디바이스내에내장된자체테스트논리회로및 디바이스내에역시내장된자체복구논리회로를포함하는내부결함검출및 복구회로를포함한다. 일실시예에서, 내장된자체테스트논리회로는메모리내의결함있는메모리셀들을자동으로식별하도록구성될수 있다. 하나이상의결함있는메모리셀들의식별시에, 내장된자체복구논리회로는결함있는셀들을메모리내의예비셀들로대체함으로써결함있는메모리셀들을자동으로복구하도록구성될수 있다. 일실시예에서, 데이터패턴들이메모리주소들및 주기적주소오프셋들의함수로서발생된다. 다른양태들이본원에기술되어있다.
摘要翻译：根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储单元。在一个实施例中，作为存储器地址和周期性地址偏移的函数产生数据模式。本文描述了其它方面。

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