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    • 24. 发明公开
    • 고속 패킷 처리를 위한 네트워크 프로세서 기반 2단계 침입탐지장치 및 방법
    • 使用网络处理器的高速分组处理的两级入侵检测系统及其方法
    • KR1020130068631A
    • 2013-06-26
    • KR1020110135926
    • 2011-12-15
    • 한국전자통신연구원
    • 최영한김덕진이성렬이만희배병철박상우윤이중
    • H04L12/26H04L12/22H04L29/06
    • H04L63/1458H04L63/0236H04L63/0245H04L63/1416
    • PURPOSE: Network processor based two-step intrusion detection device and method for high-speed packet processing are provided to perform intrusion detection using a network processor by classifying a packet into a packet header and a packet payload. CONSTITUTION: A first intrusion detector(201) performs intrusion detection with respect to a protocol field of layer3 and layer4 in the information included in a packet header of a packet transmitted to an intrusion detection device. When the intrusion is not detected, the first intrusion detector classifies the packet according to a flow. The first intrusion detector transmits the classified flow to a second intrusion detector(202). The second intrusion detector performs intrusion detection through DIP(Deep Packet Inspection) with respect to a packet payload of the packet transmitted from the first intrusion detector using a second network processor. [Reference numerals] (201) First intrusion detector; (202) Second intrusion detector; (204) First network processor; (205) Packet header invasion condition; (206) Second network processor; (207) Payloader invasion condition
    • 目的:提供基于网络处理器的两步入侵检测设备和高速分组处理方法,通过将分组分类为分组头和分组有效载荷,使用网络处理器执行入侵检测。 构成:第一入侵检测器(201)针对发送到入侵检测设备的分组的分组报头中包含的信息中的层3和层4的协议字段执行入侵检测。 当未检测到入侵时,第一个入侵检测器根据流程分类数据包。 第一入侵检测器将分类流传输到第二入侵检测器(202)。 第二入侵检测器通过使用第二网络处理器的从第一入侵检测器发送的分组的分组有效载荷通过DIP(深度分组检测)执行入侵检测。 (附图标记)(201)第一入侵检测器; (202)第二入侵检测器; (204)第一网络处理器; (205)分组报头入侵条件; (206)第二网络处理器; (207)有效载荷器入侵条件
    • 30. 发明授权
    • 회선방식 다단 상호 접속망용 스위칭 소자.
    • 用于多路互连的切换装置
    • KR1019930005844B1
    • 1993-06-25
    • KR1019900017338
    • 1990-10-29
    • 한국전자통신연구원
    • 김덕진김혁구안희일손원일임기욱윤석환
    • G06F15/16
    • The device for transmitting the control signal and the data simultaneously through the set pass comprises: a tag interpretation circuit (1) outputting the signal for a pass setting; an overlap demanding inhibit circuit (2) sending the line connecting signal and the blocking signal; a pass status storing circuit (3) storing the present set pass status by inputting the reset signal and the clock signal; an auxiliary control signal circuit (4) transfering the answer signal, the blocking signal and the control signal to the input/output port; a pass control circuit (5) controlling the connecting status of the input/output port by outputting the control signal.
    • 用于通过设定通过同时发送控制信号和数据的装置包括:标签解释电路(1),输出用于通过设置的信号; 重叠要求禁止电路(2)发送线路连接信号和阻塞信号; 通过状态存储电路(3),通过输入复位信号和时钟信号来存储当前的设定通过状态; 辅助控制信号电路(4)将应答信号,阻塞信号和控制信号传送到输入/输出端口; 通过控制电路(5),通过输出控制信号来控制输入/输出端口的连接状态。