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11. 发明公开

KR1020080069865A 비휘발성 메모리 소자 및 그 동작 방법 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：KR1020080069865A
公开(公告)日：2008-07-29
申请号：KR1020070007641
申请日：2007-01-24
申请人： 삼성전자주식회사
发明人： 김원주 , 박윤동 , 구준모 , 김석필 , 이태희
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L29/7881 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825 , H01L21/28273
摘要： A nonvolatile memory device and a method for operating the same are provided to block current flow from a unit cell to bit lines by turning off an assistant transistor so as to solve a problem that the off-cell is not read. A pair of control gate electrodes(135) are provided on a semiconductor substrate(105). A source region(140) is placed between the control gate electrodes. A pair of assistant gate electrodes(115) are recessed in the semiconductor substrate. A pair of drain regions(145) are limited to the semiconductor substrate respectively. The semiconductor substrate has a bulk wafer structure, and an epitaxial layer is formed on the bulk wafer. A pair of tunneling insulating layers(120) are placed between the semiconductor substrate and charge storage layers. A pair of blocking insulating layers(130) are placed between the control gate electrodes and the charge storage layers. A pair of gate insulating layers(110) are placed between the assistant gate electrodes and the semiconductor substrate. First and second channel regions(165,170) are connected directly by placing the control gate electrodes and the assistant gate electrodes horizontally. The drain regions are connected with bit lines(160).
摘要翻译：提供一种非易失性存储器件及其操作方法，通过关闭辅助晶体管来阻止从单元电池到位线的电流，从而解决了不读取电池的问题。一对控制栅电极（135）设置在半导体衬底（105）上。源极区域（140）被放置在控制栅电极之间。一对辅助栅极电极（115）凹入半导体衬底。一对漏极区域（145）分别限于半导体衬底。半导体衬底具有体晶片结构，并且在体晶片上形成外延层。一对隧道绝缘层（120）被放置在半导体衬底和电荷存储层之间。在控制栅电极和电荷存储层之间放置一对阻挡绝缘层（130）。一对栅极绝缘层（110）被放置在辅助栅电极和半导体衬底之间。第一和第二通道区域（165,170）通过水平放置控制栅电极和辅助栅电极而直接连接。漏极区域与位线（160）连接。

12. 发明公开

KR1020080027905A 트렌치내에 나노크리스탈 기억 소자들을 포함한 프로그래밍가능한 구조 无效
标题翻译：可编程结构，包括纳米晶体中的纳米储存元素
公开(公告)号：KR1020080027905A
公开(公告)日：2008-03-28
申请号：KR1020087002472
申请日：2006-07-21
申请人： 엔엑스피 유에스에이, 인코포레이티드
发明人： 신다로레,고리샹카엘.
IPC分类号： H01L21/8238 , H01L21/8247 , H01L21/336 , B82Y40/00
CPC分类号： H01L27/11521 , B82Y10/00 , H01L27/115 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352
摘要： A storage cell includes a semiconductor substrate (102) defining a trench (108), a bottom dielectric (110) lining the trench, and a charge storage layer on the bottom dielectric. The charge storage layer (121) includes a plurality of discontinuous storage elements (DSEs). A control gate and a top dielectric cover the DSEs. The storage cell includes a source/drain region underlying the trench. The DSEs may be silicon nanocrystals and the control gate may be polysilicon. The control gate may be recessed below an upper surface of the semiconductor substrate and an upper most of the DSEs may be vertically aligned with the control gate upper surface. The storage cell may include an oxide gap structure laterally aligned with the silicon nanocrystals adjacent the trench sidewall and extending vertically from the upper most of the silicon nanocrystals to the upper surface of the substrate. The DSEs include at least programmable two injection regions. ® KIPO & WIPO 2008
摘要翻译：存储单元包括限定沟槽（108）的半导体衬底（102），衬底衬底的底部电介质（110）和底部电介质上的电荷存储层。电荷存储层（121）包括多个不连续存储元件（DSE）。一个控制门和一个顶部电介质覆盖了DSE。存储单元包括在沟槽下面的源极/漏极区域。 DSE可以是硅纳米晶体，并且控制栅极可以是多晶硅。控制栅极可以在半导体衬底的上表面下方凹入，并且最大的DSE可以与控制栅极上表面垂直对准。存储单元可以包括与邻近沟槽侧壁的硅纳米晶体横向对齐并从最上面的硅纳米晶体垂直延伸到衬底的上表面的氧化物间隙结构。 DSE至少包括可编程的两个注入区域。 ®KIPO＆WIPO 2008

13. 发明公开

KR1020070109866A 반도체 장치 및 그 제조 방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020070109866A
公开(公告)日：2007-11-15
申请号：KR1020070044458
申请日：2007-05-08
申请人： 가부시끼가이샤 도시바
发明人： 야마모또아끼히또 , 오자와요시오
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L21/28273
摘要： A semiconductor device and a manufacturing method of the same are provided to improve data holding characteristics of a non-volatile memory and to prevent size reduction of an EEPROM(Electrically Erasable Programmable Read Only Memory) due to thin thickness of IPD(Inter-Poly-Dielectric). A gate dielectric layer(2) is formed on at least one section of a surface of a semiconductor substrate(1). At least, one first gate electrode(3) is formed on the gate dielectric layer. An inter-electrode dielectric layer(6) is formed by coating a surface of the first gate electrode. At least, a layer thickness of a part covering a part other than a part which does not come into contact with the gate dielectric layer from among a plurality of corner parts of the first gate electrode is smaller than at least a layer thickness of a part covering the corner parts which does not come into contact with the gate dielectric layer. A second gate electrode(9) is formed to cover a surface of the inter-electrode dielectric layer.
摘要翻译：提供了一种半导体器件及其制造方法，以改善非易失性存储器的数据保持特性，并且防止由于IPD的厚度（Poly-Poly- 电介质）。栅电介质层（2）形成在半导体衬底（1）的表面的至少一个部分上。至少在栅介质层上形成一个第一栅电极（3）。通过涂覆第一栅电极的表面形成电极间电介质层（6）。至少覆盖与第一栅电极的多个角部之间不与栅极电介质层接触的部分以外的部分的层的厚度小于至少一部分的层厚度覆盖不与栅极介电层接触的角部。第二栅电极（9）形成为覆盖电极间介电层的表面。

14. 发明公开

KR1020070104855A 불휘발성 반도체 메모리 失效
标题翻译：非易失性半导体存储器
公开(公告)号：KR1020070104855A
公开(公告)日：2007-10-29
申请号：KR1020070039372
申请日：2007-04-23
申请人： 가부시끼가이샤 도시바
发明人： 이찌게마사유끼 , 아라이후미따까 , 시로따리이찌로 , 야에가시도시따께 , 오자와요시오 , 야마모또아끼히또 , 미즈시마이찌로 , 사이또요시히꼬
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881 , H01L21/28141
摘要： A non-volatile memory device is provided to increase an interference effect between cells by disposing a low-k dielectric in a region mostly adjacent to floating gates. Floating gates(34,35) of first and second memory cells are composed of a first portion and a second portion disposed on the first portion and having a width narrower than that of the first portion in a direction to which a control gate(37) extends, respectively. The first portion is disposed between isolation insulating layers(32) of strip shape, and an upper surface of the isolation insulating layer is flush with an upper surface of the first portion or is lower than it. A space between the first portions of the first and second memory cells is filled with a first dielectric, and a space between the second portions is filled with a second dielectric having dielectric constant higher that the first dielectric.
摘要翻译：提供了一种非易失性存储器件，用于通过在与浮动栅极大致相邻的区域中布置低k电介质来增加单元之间的干扰效应。第一和第二存储单元的浮动栅极（34,35）由设置在第一部分上的第一部分和第二部分组成，其宽度比第一部分的宽度窄于控制栅极（37）的方向，分别延伸。第一部分设置在带状的隔离绝缘层（32）之间，隔离绝缘层的上表面与第一部分的上表面齐平或者比第一部分的上表面平齐。在第一和第二存储单元的第一部分之间的空间填充有第一电介质，并且第二部分之间的空间填充有介电常数高于第一电介质的第二电介质。

15. 发明授权

KR100763918B1 NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 无效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：KR100763918B1
公开(公告)日：2007-10-05
申请号：KR20060071570
申请日：2006-07-28
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM WON JOO , KIM SUK PIL , PARK YOON DONG
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42352 , H01L29/66621 , H01L29/7881 , H01L29/792 , H01L21/28273 , H01L21/28282
摘要： A nonvolatile memory device and a manufacturing method thereof are provided to improve the level of integration by connecting first and second channel regions with each other without an additional doping region using an improved arrangement of first and second control gate electrodes. A nonvolatile memory device includes a plurality of first control gate electrodes(145) recessed into a semiconductor substrate, a plurality of second control gate electrodes, a plurality of first storage node layers, and a plurality of second storage node layers. The plurality of second control gate electrodes(165) are arranged between adjacent first control gate electrodes. The second control gate electrodes are formed on the first control gate electrodes. The plurality of first storage layers(135) are interposed between the substrate and the first control gate electrodes. The plurality of second storage node layers are interposed between the substrate and the second control gate electrodes.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以通过使用第一和第二控制栅电极的改进布置来连接第一和第二沟道区彼此而不附加掺杂区域来提高积分电平。非易失性存储器件包括凹入半导体衬底的多个第一控制栅电极（145），多个第二控制栅电极，多个第一存储节点层和多个第二存储节点层。多个第二控制栅极电极布置在相邻的第一控制栅电极之间。第二控制栅电极形成在第一控制栅电极上。多个第一存储层（135）插入在基板和第一控制栅电极之间。多个第二存储节点层插入在基板和第二控制栅电极之间。

16. 发明公开

KR1020070078289A 비휘발성 기억 장치 및 그 제조 방법 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：KR1020070078289A
公开(公告)日：2007-07-31
申请号：KR1020060008419
申请日：2006-01-26
申请人： 삼성전자주식회사
发明人： 최용석 , 한정욱 , 전희석 , 김용태 , 양승진 , 권혁기
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L29/7881 , H01L21/76838
摘要： A nonvolatile memory device and its manufacturing method are provided to prevent the generation of punchthrough between source and drain regions in spite of a high integration degree by securing the length of a channel enough using a floating gate extended into a substrate. An active region is defined on a semiconductor substrate. A control gate electrode(56) is formed on the active region via a gate insulating layer. A floating gate(64f) is formed within the active region through the control gate electrode. The floating gate is extended into the substrate as much as a depth. A tunnel insulating layer(62) is continuously interposed at a portion between the control gate electrode and the floating gate and between the substrate and the floating gate.
摘要翻译：提供一种非易失性存储器件及其制造方法，以通过使用延伸到衬底中的浮动栅极来确保足够的沟道的长度，来防止在源极和漏极区域之间产生穿透。在半导体衬底上限定有源区。控制栅电极（56）经由栅极绝缘层形成在有源区上。通过控制栅电极在有源区内形成浮栅（64f）。浮动栅极延伸到衬底中的深度。隧道绝缘层（62）被连续插入在控制栅极电极和浮动栅极之间以及衬底和浮动栅极之间的部分。

17. 发明授权

KR100735534B1 NANO CRYSTAL NONVOLATILE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD THEREOF 无效
标题翻译：纳米晶体非线性半导体集成电路器件及其制造方法
公开(公告)号：KR100735534B1
公开(公告)日：2007-06-28
申请号：KR20060030581
申请日：2006-04-04
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHOI SAM JONG , CHO KYOO CHUL , CHOI SOO YEOL , KIM YONG KWON , PARK YOUNG SOO , IHN CHAN KOOK , PARK HAE JIN , KIM SANG SIG
IPC分类号： H01L27/115
CPC分类号： H01L21/265 , B82Y10/00 , G11C2216/06 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L29/1037 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66825 , H01L29/7881 , H01L29/7885 , H01L29/7887
摘要： A nano crystal nonvolatile semiconductor integrated device and a manufacturing method thereof are provided to dramatically reduce leakage of trapped charges by using a nano crystal as a charge trap site. An insulating layer(110b) is formed on a substrate(100). The insulating layer has an energy band gap in excess of 5 eV and a dielectric constant in excess of 7. Ions for forming a nano crystal(130_NC) are injected in the insulating layer with ion implantation energy of 7 to 10 KeV. An annealing process is performed to form a charge trap layer(150a) where a plurality of charge trap nano crystal are embedded. An annealing process is performed before the ion injection for forming the nano crystal.
摘要翻译：提供了一种纳米晶体非易失性半导体集成器件及其制造方法，以通过使用纳米晶体作为电荷陷阱位点来显着减少捕获电荷的泄漏。绝缘层（110b）形成在基板（100）上。绝缘层具有超过5eV的能带隙和超过7的介电常数。用于形成纳米晶体的离子（130_NC）以7至10KeV的离子注入能量注入绝缘层中。进行退火处理以形成其中嵌入多个电荷陷阱纳米晶体的电荷陷阱层（150a）。在用于形成纳米晶体的离子注入之前进行退火处理。

18. 发明公开

KR1020070010418A 2비트 메모리 셀을 포함하는 비휘발성 반도체 집적 회로장치 및 그 제조 방법 失效
标题翻译：具有2BIT存储单元的非线性半导体集成电路器件及其制造方法
公开(公告)号：KR1020070010418A
公开(公告)日：2007-01-24
申请号：KR1020050064963
申请日：2005-07-18
申请人： 삼성전자주식회사
发明人： 김일권
IPC分类号： H01L27/115 , B82Y10/00
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/42332 , H01L29/42336
摘要： A non-volatile semiconductor integrated circuit device including a 2-bit memory cell is provided to enable a stabilized local program and stably store 2-bit information by increasing the length of an effective channel by a step recess channel. A source/drain(160S,160D) is formed in a semiconductor substrate(100). A step recess channel(110) is formed between the source and the drain. A trap structure includes a plurality of charge trap nano-crystals(135_NC) on the step recess channel region. A gate(150) is formed on the trap structure. The recess channel is formed at the source in a read operation. Both sides of the trap structure are recessed toward the inside of the gate.
摘要翻译：提供了包括2位存储单元的非易失性半导体集成电路器件，以便能够通过逐步凹槽通道增加有效通道的长度来实现稳定的本地程序并稳定地存储2位信息。源极/漏极（160S，160D）形成在半导体衬底（100）中。在源极和漏极之间形成台阶凹槽（110）。陷波结构包括在台阶凹槽沟道区域上的多个电荷陷阱纳米晶体（135_NC）。在捕集器结构上形成一个栅极（150）。在读取操作中，在源处形成凹槽。陷阱结构的两侧朝向门的内侧凹陷。

19. 发明公开

KR1020060118898A 반도체 기억 소자들 및 그 제조방법들 无效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：KR1020060118898A
公开(公告)日：2006-11-24
申请号：KR1020050041331
申请日：2005-05-17
申请人： 삼성전자주식회사
发明人： 김시은 , 백승재 , 여인석 , 윤홍식 , 훠종량
IPC分类号： H01L27/10 , H01L27/108
CPC分类号： H01L29/42328 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A semiconductor memory device and a manufacturing method thereof are provided to improve short channel effect of a sensing transistor by arranging a control gate line for controlling the sensing transistor. A body layer pattern(22) is located on a substrate(20). A source region(24) and a drain region(26) are located in the body layer pattern to be separated from each other. A data line(30) crosses an upper portion of a channel region(28) between the source region and the drain region. An MTJ(Multiple Tunnel Junction) barrier layer(32) is arranged between the gate line and the channel line. A floated storage node(34) is located between the channel region and the MTJ barrier layer. A first control gate line(38) crosses an upper portion of the data line and covers both sidewalls of the storage node and both sidewalls of the MTJ barrier layer. A second control gate line(42) is located on a lower portion of the channel region and crosses a lower portion of the body layer pattern.
摘要翻译：提供一种半导体存储器件及其制造方法，用于通过布置用于控制感测晶体管的控制栅极线来改善感测晶体管的短沟道效应。体层图案（22）位于基底（20）上。源区域（24）和漏极区域（26）位于体层图案中以彼此分离。数据线（30）与源极区域和漏极区域之间的沟道区域（28）的上部相交。栅极线和通道线之间布置有MTJ（多隧道结）阻挡层（32）。浮动存储节点（34）位于通道区域和MTJ阻挡层之间。第一控制栅极线（38）跨越数据线的上部并且覆盖存储节点的两个侧壁和MTJ阻挡层的两个侧壁。第二控制栅极线（42）位于沟道区的下部并与本体层图案的下部交叉。

20. 发明授权

KR100628419B1 개선된 게이트 전극을 포함하는 불휘발성 반도체 기억 장치 失效
标题翻译：非线性半导体存储器件，包括改进的栅极电极
公开(公告)号：KR100628419B1
公开(公告)日：2006-09-28
申请号：KR1020030066807
申请日：2003-09-26
申请人： 가부시끼가이샤 도시바
发明人： 아라이후미따까 , 마쯔나가야스히꼬 , 사꾸마마꼬또 , 시로따리이찌로 , 시미즈아끼라
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： 반도체 기판 상에 게이트 절연막을 개재하여 부유 게이트가 형성된다. 상기 반도체 기판 내의 상기 부유 게이트의 양쪽에 소스 또는 드레인 영역으로서 확산층이 형성된다. 상기 양쪽 확산층에 대향하여 상기 부유 게이트의 양쪽에 상기 부유 게이트를 구동하기 위한 제1 및 제2 제어 게이트가 게이트간 절연막을 개재하여 형성된다.
게이트 절연막, 부유 게이트, 불휘발성 반도체 기억 장치, 게이트 전극, 메모리 셀

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