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    • 3. 发明授权
    • 주(main) CPU 감시장치
    • 主CPU监控设备
    • KR1019930001793B1
    • 1993-03-13
    • KR1019890020567
    • 1989-12-30
    • 한국전자통신연구원주식회사 케이티
    • 홍재환송광석
    • G06F11/00
    • The apparatus detects and processes faults in the main CPU used for a full electronic switching system. The main CPU comprises a synchronous buffer (1) for synchronizing external signals of the CPU; the main CPU (2), connected with the synchronous buffer (1), processing general data; another CPU (4) for monitoring the main CPU (2); a synchronous circuit (3) generating one address strobe signal (AS); a data buffer (6) for inputing data for the detecting CPU (4); a comparator (5) comparating the addresses between the two CPUs (2,4), detecting if an abnormal state occurs in the main CPU (2), and rapidly transmitting the detected data.
    • 该装置检测并处理用于全电子交换系统的主CPU中的故障。 主CPU包括用于同步CPU的外部信号的同步缓冲器(1) 主CPU(2)与同步缓冲器(1)连接,处理一般数据; 用于监视主CPU(2)的另一个CPU(4); 产生一个地址选通信号(AS)的同步电路(3); 用于输入检测CPU(4)的数据的数据缓冲器(6); 比较器(5),比较两个CPU(2,4)之间的地址,检测主CPU(2)中是否发生异常状态,并迅速发送检测到的数据。
    • 7. 发明授权
    • 이중화된 프로세서에서의 데이타 전송장치
    • 数据传输设备在冗余处理器上
    • KR1019930006234B1
    • 1993-07-09
    • KR1019900022785
    • 1990-12-31
    • 주식회사 케이티한국전자통신연구원
    • 홍재환송광석장길주
    • H04M3/22
    • The circuit for increasing data transfer speed in the dual processor system by using direct standby processor memory access by the active processor comprises: system bus buffer 1 (321) for generating a system bus synchronized control signal; control signal driver unit 1 (324) for interfacing both processors and transferring control signals from the system bus buffer 1 to the extended bus; transmission signal control buffer unit (325) to output extended bus access success or fail signal; transmission control unit (323) and control signal driver unit 2 (322) for detecting one clock cycle termination.
    • 用于通过使用主动处理器的直接待机处理器存储器访问来增加双处理器系统中的数据传输速度的电路包括:用于产生系统总线同步控制信号的系统总线缓冲器1(321) 控制信号驱动器单元1(324),用于将两个处理器接口并将控制信号从系统总线缓冲器1传送到扩展总线; 传输信号控制缓冲器单元(325),用于输出扩展总线访问成功或失败信号; 传输控制单元(323)和用于检测一个时钟周期终止的控制信号驱动单元2(322)。