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    • 4. 发明专利
    • Signal processor
    • JP2004201161A
    • 2004-07-15
    • JP2002369373
    • 2002-12-20
    • Sony Corpソニー株式会社
    • KOBAYASHI MASAYAGOSEKI SHOZO
    • H04N11/16
    • PROBLEM TO BE SOLVED: To provide a signal processor capable of accurately detecting frame or field switching timing with a simple configuration even when the number of pieces of pixel data for one frame image or one field image obtained by sampling a frame image signal or field image signal on the basis of a reference signal of a prescribed frequency is a number that brings about a remainder in a division by the number of pieces of pixel data for one line.
      SOLUTION: A memory control circuit 15 detects a trigger used for sampling in a clock signal CLK in each of line periods, detects first timing at which lines are switched on the basis of a discrete value showing the number of times of detecting the trigger, and holds the number of times which corresponds to the remainder and a discrete value from detecting the trigger till detecting the next trigger in a process of detecting the trigger about all lines in one frame or field.
      COPYRIGHT: (C)2004,JPO&NCIPI
    • 10. 发明专利
    • METHOD AND SYSTEM FOR CORRECTING CONTOUR
    • JPH11313337A
    • 1999-11-09
    • JP3269199
    • 1999-02-10
    • IKEGAMI TSUSHINKI KK
    • KASHIMURA NAOKI
    • H04N11/16H04N9/64H04N9/68
    • PROBLEM TO BE SOLVED: To suppress an area cross color that is unable to be suppressed at a receiver side by conducting two-dimensional contour along with plural straight lines that are drawn through positions of a color subcarrier frequency appearing a both left and right sides on the lateral axis around the origin, through positions of the color subcarrier frequency appearing discretely along with a straight line in parallel with the longitudinal axis and not through the origin. SOLUTION: A color image signal of the PAL system that is fed to an input terminal 11 and whose contour is to be corrected is divided into two, the one is fed to a 1st 2H delay circuit 12 and the signal that is outputted from this delay circuit and delayed by 2H is fed to a 2nd 2H delay circuit 13. The image signal that is outputted from the 2nd 2H delay circuit 13 and delayed by 4H is divided into two, and the one is fed to a 4th 2T delay circuit 15. Furthermore, the image signal that is outputted from the 1st 2H delay circuit 12 and delayed by 2H is fed to a 5th 1T delay circuit 16. The image signal that is outputted from a 3rd 2T delay circuit 14 and delayed by 2T is fed to a 1st gain adjustment circuit 17.