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3. 发明专利

JPS5926136B2 JPS5926136B2 - 失效
公开(公告)号：JPS5926136B2
公开(公告)日：1984-06-25
申请号：JP1017175
申请日：1975-01-25
申请人： Nippon Electric Co
发明人： KATO KOTARO , TAKAI HARUKI
IPC分类号： H04L1/00 , H03K3/86 , H03K5/00 , H03L7/00 , H03L7/06 , H04B7/155 , H04J3/06 , H04L5/22 , H04L7/02 , H04L7/027
CPC分类号： H04L7/027

5. 发明专利

JPS5317250A CIRCUIT FOR ALTERING PULSE DURATION AND PERIOD 失效
公开(公告)号：JPS5317250A
公开(公告)日：1978-02-17
申请号：JP9151776
申请日：1976-07-31
申请人： TAMURA ELECTRIC WORKS LTD
发明人： YUBASHI KEIICHI
IPC分类号： H03K3/017 , H03K3/72 , H03K3/86 , H03K5/00 , H03K5/156 , H03K23/00 , H03K23/64

6. 实用新型

JPS518350Y2 失效
公开(公告)号：JPS518350Y2
公开(公告)日：1976-03-05
申请号：JP6472571
申请日：1971-07-23
IPC分类号： H03K3/02 , H03K3/03 , H03K3/64 , H03K3/66 , H03K3/70 , H03K3/86 , H03K5/13 , H03K5/14 , H03K5/153

7. 发明专利

JP4105966B2 Calculation type continuous variable frequency oscillation circuit 有权
公开(公告)号：JP4105966B2
公开(公告)日：2008-06-25
申请号：JP2003072223
申请日：2003-03-17
申请人：四国計測工業株式会社
发明人：合田俊午 , 横山隆利
IPC分类号： H03K3/86 , H03K19/173

8. 发明专利

JP2000101404A VARIABLE DELAY CIRCUIT 失效
公开(公告)号：JP2000101404A
公开(公告)日：2000-04-07
申请号：JP26453098
申请日：1998-09-18
申请人： ADVANTEST CORP
发明人： NAKANE YASUHIKO
IPC分类号： G11C11/4076 , H03K3/86 , H03K5/13 , H03K5/131
摘要： PROBLEM TO BE SOLVED: To share two pulse delays by using one system delay circuit and to generate two delay pulses which are delayed for a specified time respectively by dynamically switching two delay setting data of A and B for every bits of one system variable delay circuit and outputting the delay pulses, which are delayed for the specified time with the corresponding delay-setting data. SOLUTION: Upon the reception of delay setting data HR1 and HR2 from two systems, only one system variable delay means comprising (m)-stage bit unit delay means 101, 102, etc., two pulse separating means 300, data effective registers 18 and 19 and A and B registers R101 and R102 is used to output a set pulse signal SP10, which is delayed for a specified time and a reset pulse signal SP11. The bit unit delay means 101, 102, etc., comprises a unit delay element 200, a passing pulse control means 10, a different value detecting means 21 and a priority detecting means 22. Consequently, the two delay setting data HR 1 and HR2 are received, and a delay can be made by one system variable delay means.

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