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    • 1. 发明专利
    • XY MATRIX DISPLAY DEVICE
    • JPH01207792A
    • 1989-08-21
    • JP3378788
    • 1988-02-16
    • DEIKUSHII KK
    • IGARASHI TOYOAKIKISHI TOMOKATSUYOSHIZAWA TAKAHITOMORITA MINORUENDO JOICHI
    • G09G3/20
    • PURPOSE:To easily allow the title device to correspond to external clocks or the like with different formats by providing the device with address counters for counting up external clocks by timing signal generating circuits and generat ing address signals to be supplied to memories. CONSTITUTION:The address counters 33, 35 are reset by external synchronizing signals, the contents of the counters 33, 35 are counted up by external clocks having frequencies higher than that of the external synchronizing signals, address signals from the counters 33, 35 are supplied to the memories 51, 52, and an internal clock and an internal synchronizing signal are outputted from the memories 51, 52. The internal clock and the internal synchronizing signal are supplied to a driving circuit 20 together with internal display data, the XY matrix display device is driven by the driving circuit 20 and display is executed on the basis of the internal display data. Consequently, the device can be easily allowed to correspond to external clocks or the like with different formats.
    • 2. 发明专利
    • SEPARATION CIRCUIT FOR HORIZONTAL SYNCHRONIZING SIGNAL
    • JPS63263978A
    • 1988-10-31
    • JP9906687
    • 1987-04-22
    • DEIKUSHII KK
    • FUJITA TOYOMI
    • H04N5/10
    • PURPOSE:To surely separate a horizontal synchronizing signal from a composite signal by supplying an edge signal to a horizontal synchronizing signal reproducing circuit, inhibiting the operation of an FF circuit for a prescribed time from the rear edge of the composite synchronizing signal to output a reproduced horizontal synchronizing signal. CONSTITUTION:The edge signal from an edge detection circuit 2 detecting the front edge and the rear edge of the composite synchronizing signal is fed to the horizontal synchronizing signal reproducing circuit 3. Then the operation of the FF circuit 3a is inhibited for a prescribed time selected in response to the relative position of horizontal and vertical synchronizing signals shorter than a time obtained by subtracting the pulse width from the period of the horizontal synchronizing signal from the rear edge of the composite synchronizing signal by the inhibition signal generating circuit 4 and the reproduced horizontal synchronizing signal separated from the composite synchronizing signal is outputted from the horizontal synchronizing signal reproducing circuit 3.
    • 3. 发明专利
    • MANUFACTURE OF ELECTRODE FORMING, MEMBER OF DISCHARGE INDICATOR
    • JPH01251534A
    • 1989-10-06
    • JP7864388
    • 1988-03-31
    • DEIKUSHII KK
    • ISHIKAWA MASATAKE
    • H01J9/02H01J17/49
    • PURPOSE:To aim at facilitating control of width and thickness of electrodes and partitions by filling depressions having a formed prescribed pattern with an insulation material and removing a photo-resistive layer on a conductive layer. CONSTITUTION:A conductive layer 2A is formed on a substrate 1, a photo-resist layer 3 is applied and formed on the conductive layer 2A, light is radiated to the photo-resist layer 3 through an optical mask 4 having a prescribed pattern and the photo-resist layer 3 irradiated with light is removed and subjected to etching treatment. Then, after a part 3b of the photo-resist layer 3 and a part of the underlaying conductive layer 2A are removed to form depressions having the prescribed pattern, the depressions are filled with an insulation material 5A and the photo-resist layer 3 over the conductive layer 2A is removed to produce, on the substrate 1, electrodes 2 having the prescribed patterns and partitions 5 having the prescribed patterns therebetween. With this procedure it is possible to facilitate control of the width and thickness of electrodes and partitions.
    • 5. 发明专利
    • DRIVING DEVICE FOR XY MATRIX DISCHARGING DISPLAY DEVICE
    • JPH025084A
    • 1990-01-09
    • JP15621588
    • 1988-06-24
    • DEIKUSHII KK
    • AWAJI NORIYUKIFUJITA TOYOMI
    • G09G3/28G09G3/291G09G3/296
    • PURPOSE:To obtain the display device which has high brightness and high light emission efficiency without using memory effect by placing alternate cathodes in a discharge ready state at constant intervals and making respective display cells illuminate alternately according to data corresponding to the cathodes. CONSTITUTION:With scanning signals generated by scanning signal generating means OS, FK1 - FK4, and 21 - 24, (n) scanning electrodes which are selected in order among plural scanning electrodes K1 - K4 at a specific period are placed alternately in the discharge ready state at prescribed repetitive frequency in a prescribed period shorter than said specific period. Further, data switching and supplying means Fa1 - Fa4, Fb1 - Fb4, Fc1 - Fc4, M, Fd, 1 - 8, and 9 - 12 switch and supply two kinds of data corresponding to the (n) scanning electrodes selected in order in each prescribed period to plural data electrodes A1 - A4 alternately in synchronism with the scanning signals. Consequently, the light emission brightness and light emission efficiency of an XY plasma display device are both improved.
    • 6. 发明专利
    • XY MATRIX DISPLAY DEVICE
    • JPH01209494A
    • 1989-08-23
    • JP3455588
    • 1988-02-17
    • DEIKUSHII KK
    • IGARASHI TOYOAKIKISHI TOMOKATSUYOSHIZAWA TAKAHITOMORITA MINORUENDO JOICHI
    • G09G3/20
    • PURPOSE:To easily and automatically select and output an external clock in different modes, an internal clock which is adapted to an external synchronizing signal, and an internal synchronizing signal by selecting a pair of the internal clock and internal synchronizing signal generated by a timing signal generating circuit according to the decision outputs of polarity deciding circuits. CONSTITUTION:The timing signal generating circuit is so constituted as to generate internal clocks and internal synchronizing signals. Then polarity deciding circuits 57 and 58 are provided which decide the polarities of horizontal and vertical synchronizing signals constituting an external synchronizing signal. A pair of an internal clock and an internal synchronizing signal generated by the timing signal generating circuit are selected according to the decision outputs of the polarity deciding circuits 57 and 58. Consequently, internal clocks and internal synchronizing signals adapted to the external clock and external synchronizing signal in different modes are selected and outputted easily and automatically without alternating the timing signal generating circuit.
    • 8. 发明专利
    • XY MATRIX DISPLAY DEVICE
    • JPH01207793A
    • 1989-08-21
    • JP3378888
    • 1988-02-16
    • DEIKUSHII KK
    • IGARASHI TOYOAKIKISHI TOMOKATSUYOSHIZAWA TAKAHITOMORITA MINORUENDO JOICHI
    • G09G3/20
    • PURPOSE:To easily allow the title device to correspond to external clocks, external synchronizing signals, internal clocks, and internal synchronizing signals having respectively different formats by arranging a 1st address counter to be reset by a 1st external synchronizing signal and a 2nd address counter to be reset by a 2nd external synchronizing signal in a timing signal generating circuit. CONSTITUTION:The timing signal generating circuit has a 1st memory 51 storing a 1st internal synchronizing signal and a 1st internal clock, the 1st address counter 33 to be reset by the 1st external synchronizing signal, counted up by a 1st external clock and generating an address signal to be supplied to the 1st memory 51 and the 2nd address counter 35 to be counted up by a 2nd external clock and generating an address signal to be supplied to a 2nd memory 52. Consequently, the circuit is simplified, the packaging area of the circuit can be reduced and the device can be easily allowed to correspond to the external clocks, external synchronizing signals and internal clocks and internal synchronizing signals having respectively different formats without changing the timing signal generating circuit itself.
    • 9. 发明专利
    • DISPLAY CONTROLLER
    • JPH0287188A
    • 1990-03-28
    • JP23850288
    • 1988-09-22
    • IBM JAPANDEIKUSHII KK
    • SEKIYA KAZUOSHIRAISHI YUICHIENDO JOICHIIGARASHI TOYOAKI
    • G09G3/20G09G3/291G09G3/296
    • PURPOSE:To display an image plane consisting of an optional number of lines than the number of display liens of a display device at an optional vertical position on a display panel at all times by providing a means which generates a signal for varying and setting the number of blank feeding shift clock pulses, feeding lines with the blank feeding shift clock, and making no display in the blank feeding period. CONSTITUTION:A generation part 60 for a horizontal synchronizing signal as an interface signal to a matrix display device consists of a generating circuit 61 for the blank feeding shift clock, a generating circuit 62 for pulses of frequency which is an (n) times as high as a horizontal synchronizing signal, and a kick circuit 63 for the generating circuit 61. In this case, lines are fed on the display device by as many as the blank feeding shift clock pulses in the blank feeding period and no display is made throughout the period. For the purpose, this blank feeding period is so set that when the number of lines on the image plane is smaller than that of the display panel, parts of unnecessary lines at the upper and lower part of the display panel are fed in blank, thereby displaying the image plane in the center. Further, the image plane can easily be displayed at an optical desired vertical position.