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1. 发明专利

JP2011023927A Digital filter and program 审中-公开
标题翻译：数字滤波器和程序
公开(公告)号：JP2011023927A
公开(公告)日：2011-02-03
申请号：JP2009166527
申请日：2009-07-15
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： H03H17/04
摘要： PROBLEM TO BE SOLVED: To perform a digital filter operation with high accuracy without increasing a hardware scale.
SOLUTION: The digital filter performs, when a filter coefficient multiplied to a signal to be processed of an IIR filter operation or a filter coefficient multiplied to a signal generated in its execution process is a value near 1 or -1, performs the IIR filter operation using 1 or -1 as a new filter coefficient, performs an IIR filter operation using difference between the filter coefficient and the new filter coefficient as a new filter coefficient, and subtracts the latter operation results from the former operation results to output the results. In the latter operation, the operation results are obtained by performing a filter operation using a value obtained by multiplying the difference by an integer value which is large according as its number of effective bits is small as the filter coefficient and after that, further performing division by the integer value.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在不增加硬件规模的情况下，以高精度执行数字滤波操作。解决方案：当与要处理的IIR滤波器操作的信号相乘的滤波器系数或与其执行过程中生成的信号相乘的滤波器系数为1或-1时，数字滤波器执行使用1或-1作为新的滤波器系数的IIR滤波器操作，使用滤波器系数和新的滤波器系数之间的差作为新的滤波器系数执行IIR滤波操作，并且从前一个运算结果中减去后一运算结果，输出结果。在后一种操作中，通过使用通过将差乘以与有效位数相比较大的整数值作为滤波器系数而获得的值来进行滤波操作，然后进一步执行除法乘整数值。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2006203505A Content distributing system, server, user terminal and program 审中-公开
标题翻译：内容分发系统，服务器，用户终端和程序
公开(公告)号：JP2006203505A
公开(公告)日：2006-08-03
申请号：JP2005012472
申请日：2005-01-20
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： G06F13/00 , H04N7/173 , H04N21/4788
摘要： PROBLEM TO BE SOLVED: To reduce load of a distribution server in a content distribution system where an animation or the like is distributed. SOLUTION: When a distribution request of a content such as the animation is supplied to the distribution server 110 from one of user terminals 120 to 190, decoding key data for decoding ciphered content data is supplied to the user terminal from the distribution server 110, and a site list where other user terminals which previously down-load enciphered content data are listed is supplied. Content data is transmitted/received between the user terminals based on the site list. Thus, load of the distribution server 110 is reduced. A charging amount is discounted on the user terminal transmitting content data to the other user terminal. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：减少分发动画等的内容分发系统中的分发服务器的负载。解决方案：当诸如动画的内容的分发请求从用户终端120到190之一提供给分配服务器110时，用于解码加密内容数据的解码密钥数据从分发服务器提供给用户终端 110，以及其中列出了先前下载了加密内容数据的其他用户终端的站点列表。基于站点列表在用户终端之间发送/接收内容数据。因此，分发服务器110的负载减少。用户终端向其他用户终端发送内容数据的费用是折扣的。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005136626A Audio signal processor 有权
标题翻译：音频信号处理器
公开(公告)号：JP2005136626A
公开(公告)日：2005-05-26
申请号：JP2003369330
申请日：2003-10-29
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI , TODA HIROYUKI , MURAKI YASUYUKI
IPC分类号： H04S1/00 , H04S7/00
摘要： PROBLEM TO BE SOLVED: To provide an audio signal processor which reduces power consumption and performs various signal processings. SOLUTION: A data path part 30 receives voice data A and B, and performs signal processing to those data by time-division control. A mode register 50 stores mode information to designate signal processing to be performed. A state machine part 40 successively generates a control signal, to make the data path part 30 execute one or more arithmetic processings configuring signal processings to be designated by mode information stored in the mode register 50. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供降低功耗并执行各种信号处理的音频信号处理器。解决方案：数据路径部分30接收语音数据A和B，并通过时分控制对这些数据执行信号处理。模式寄存器50存储用于指定要执行的信号处理的模式信息。状态机部40依次生成控制信号，使数据路径部30执行一个或多个运算处理，配置由模式寄存器50中存储的模式信息指定的信号处理。（C）2005， JPO＆NCIPI

4. 发明专利

JP2004227501A Data transfer controller and method 审中-公开
公开(公告)号：JP2004227501A
公开(公告)日：2004-08-12
申请号：JP2003017681
申请日：2003-01-27
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： G06F12/00 , G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller by which occurrence frequency of interruption to a central processing unit is reduced without restricting the storage capacity of a buffer memory housed in a peripheral module at a transfer destination.
SOLUTION: The data transfer controller for controlling data transfer between a main memory having arbitrary storage capacity and first-in/first-out allowed to function as a buffer for data transfer housed in the peripheral module comprises: a transfer frequency register 303 setting a value being the value indicative of the transfer frequency of the data and complying with the storage capacity of the first-in/first-out and a transfer frequency register 304 setting a value complying with the amount of the data stored on the main memory, and controls the data transfer based on the value of the transfer frequency register 303 and outputs an interruption signal to the central processing unit based on the value of the transfer frequency register 304.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2008178049A Sampling frequency conversion apparatus 有权
标题翻译：采样频率转换装置
公开(公告)号：JP2008178049A
公开(公告)日：2008-07-31
申请号：JP2007012076
申请日：2007-01-22
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： H03H17/00
CPC分类号： H03H15/02
摘要： PROBLEM TO BE SOLVED: To perform sampling frequency conversion without incurring an interpolation arithmetic error even if a sampling frequency requested by a post-stage device becomes equal to or higher than a sampling frequency of an input sample.
SOLUTION: A control unit 1a updates phase information indicating an arithmetic request signal CRQ and a phase of an interpolation sample to be generated synchronously with a main clock ϕm of a double frequency as high as an input sampling frequency f1 and when the phase information satisfies predetermined conditions, generates an arithmetic command signal. An interpolation unit 2a calculates an interpolation sample (y) using N pieces of even-numbered interpolation coefficients in 2N pieces of interpolation coefficients for 2Nth-order interpolation when the arithmetic command signal is generated in an even-numbered term, and calculates the interpolation sample (y) using N pieces of odd-numbered interpolation coefficients when the arithmetic command signal is generated in an odd-numbered term.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使后级装置要求的采样频率变得等于或高于输入样本的采样频率，也可以进行采样频率转换而不引起插值算术误差。解决方案：控制单元1a更新指示与作为输入采样频率f1的双倍频率的主时钟φm同步地生成的运算请求信号CRQ的相位信息和内插采样的相位，并且当相位信息满足预定条件，产生算术指令信号。内插单元2a在偶数项产生算术指令信号时，使用N个N次内插系数的2N次内插系数，计算内插样本（y），并计算插补样本（y）在奇数项中产生算术指令信号时使用N个奇数插值系数。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008125004A Class-d amplifier 有权
标题翻译： CLASS-D放大器
公开(公告)号：JP2008125004A
公开(公告)日：2008-05-29
申请号：JP2006309485
申请日：2006-11-15
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI , MORISHIMA MORIHITO
IPC分类号： H03F1/00 , H03F3/217 , H03M5/08 , H03M7/32
摘要： PROBLEM TO BE SOLVED: To provide a data processing apparatus such as a class-D amplifier circuit reducing manufacturing costs by reducing a size and the number of components, and improving operability by facilitating waveform setting or adjustment with flexibility in constructing a system.
SOLUTION: A class-D amplifier 100 is adapted to generate cosine wave data with which an output voltage of an LPF 190 is not rapidly changed, as a PWM signal for the LPF 190 during a starting period or an ending period, apply noise shaping and modulate the cosine wave data into a PWM signal while selectively switching them with inputted data such as sound data to be amplified, and output the signal to the LPF 190.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供诸如D类放大器电路之类的数据处理装置，通过减小组件的尺寸和数量来减少制造成本，并且通过在构造系统方面具有灵活性便利波形设置或调整来提高可操作性。解决方案：D类放大器100适于产生余弦波数据，LPF 190的输出电压不会快速改变，因为LPF 190在开始周期或结束周期期间的PWM信号适用噪声整形并将余弦波数据调制成PWM信号，同时用输入的数据（例如待放大的声音数据）选择性地切换它们，并将信号输出到LPF 190.（C）2008，JPO＆INPIT

7. 发明专利

JP2008085923A Digital filter 审中-公开
标题翻译：数字滤波器
公开(公告)号：JP2008085923A
公开(公告)日：2008-04-10
申请号：JP2006266139
申请日：2006-09-28
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： H03H17/04 , H03H17/02
摘要： PROBLEM TO BE SOLVED: To cause a digital filter to make computation with an accuracy of computation adapted to conditions of an execution of filtering-processing and avoid needless electrical power consumption. SOLUTION: Filter coefficients in a coefficient storing section 200 are rewritable via an interface 300 under control of a coefficient rewriting control section 401. Data path section 100 executes computation for applying filtering-processing using the filter coefficients in the coefficient storing section 200 to an input audio sample x(n). A filtering-processing control section 402 is means for controlling computation of the data path section 100, and makes selection of whether the single precision arithmetic or double precision arithmetic is to be executed in dependence on the filter coefficient stored in the coefficient storing section 200. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：使数字滤波器以与执行滤波处理的条件相适应的计算精度进行计算，并避免不必要的电功率消耗。解决方案：在系数重写控制部分401的控制下，系数存储部分200中的滤波器系数可经由接口300重写。数据路径部分100执行使用系数存储部分200中的滤波器系数应用滤波处理的计算到输入音频样本x（n）。滤波处理控制部分402是用于控制数据路径部分100的计算的装置，并且根据存储在系数存储部分200中的滤波器系数来选择是否要执行单精度算术或双精度算术。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007325100A Digital signal processing apparatus 有权
标题翻译：数字信号处理设备
公开(公告)号：JP2007325100A
公开(公告)日：2007-12-13
申请号：JP2006154859
申请日：2006-06-02
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： H03H17/02
摘要： PROBLEM TO BE SOLVED: To provide a digital signal processing apparatus in which an input signal can be outputted after applying a plurality of kinds of signal processing thereto and property of each of signal processings can be individually confirmed.
SOLUTION: A data path unit 100 comprises an arithmetic function for signal processing. A control unit 200 defines an impulse signal outputted from an impulse generating circuit 101 as a signal to be processed, in place of an input digital audio signal from the outside, in a test mode and the data path unit 100 applies only signal processing selected from among the plurality of kinds of signal processing to the signal to be processed in each sampling period.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种数字信号处理装置，其中可以在施加多种信号处理之后输出输入信号，并且可以单独地确认每个信号处理的属性。解决方案：数据路径单元100包括用于信号处理的算术功能。控制单元200在测试模式中定义从脉冲发生电路101输出的脉冲信号作为来自外部的输入数字音频信号，并且数据路径单元100仅应用从在每个采样周期中对要处理的信号的多种信号处理中。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2014228915A データ処理装置有权
标题翻译：数据处理设备
公开(公告)号：JP2014228915A
公开(公告)日：2014-12-08
申请号：JP2013105872
申请日：2013-05-20
申请人：ヤマハ株式会社 , Yamaha Corp
发明人： NISHIOKA NAOTOSHI
IPC分类号： G06F12/00
CPC分类号： G06F13/18 , G06F13/1663 , G06F13/1668
摘要：【課題】高い優先順位のメモリコマンドの発行数を抑制してメモリアクセス制御を高効率化し、簡略な構成で高スループット及び短レイテンシを実現したデータ処理装置を提供する。【解決手段】データ処理装置は、複数のバスマスタ10とDRAMコントローラとを備える。複数のバスマスタ10の各々は、DRAMに対するアクセスを指定するメモリコマンドを発行する処理部11と、データバッファ12,13と、データバッファ12,13の空き容量に応じて、メモリコマンドの優先順位を示す優先順位情報を当該メモリコマンドに対応づけて生成する第1及び第2の検出回路14,15とを備える。DRAMコントローラは、複数のバスマスタ10の各々が発行したメモリコマンドの処理順序を、当該メモリコマンドに対応する優先順位情報に基づいて決定する。【選択図】図2
摘要翻译：要解决的问题：提供一种数据处理装置，其以高优先级的方式抑制发出的存储器命令的数量，以高效率执行存储器访问控制，并且通过简单的配置实现高吞吐量和短延迟。解决方案：一种数据处理装置，包括：多个总线主机10; 和DRAM控制器。多个总线主机10中的每一个包括：处理单元11，用于发出指定对DRAM的访问的存储器命令; 数据缓冲器12和13; 以及第一和第二检测电路14和15，其通过根据数据缓冲器12和13的空闲容量使信息对应于存储器命令来生成表示存储器命令的优先级的优先级信息.RAM控制器确定顺序基于与存储器命令相对应的优先级信息来处理由多个总线主机10中的每一个发出的存储器命令。

10. 发明专利

JP2014170262A Bus module and data processor 审中-公开
标题翻译：总线模块和数据处理器
公开(公告)号：JP2014170262A
公开(公告)日：2014-09-18
申请号：JP2013040285
申请日：2013-03-01
申请人： Yamaha Corp , ヤマハ株式会社
发明人： NISHIOKA NAOTOSHI
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To shorten an access time to be spent on reading data from a memory which operates at a low speed even when a cache memory is not incorporated in a plurality of bus masters.SOLUTION: A bus module includes: a primary cache memory and a cache controller. When a read command received from each bus master is for a first memory, the cache controller executes processing (S8) of determining whether or not the data designated by the read command are stored in the primary cache memory, and when the data are not stored in the primary cache memory (S8: NO), executes processing (S9) of determining whether or not the data are stored in a secondary cache memory, and when the data are not stored in the secondary cache memory (S9: NO), executes processing (S10) of reading the data from the first memory, and processing (S13, S17) of storing the data in the secondary cache memory and the primary cache memory and processing (S18) of transmitting the data to a bus master.
摘要翻译：要解决的问题：即使当高速缓冲存储器未被并入多个总线主机中时，缩短从低速操作的存储器读取数据的访问时间。解决方案：总线模块包括：主缓存内存和缓存控制器。当从每个总线主机接收到的读取命令用于第一存储器时，高速缓存控制器执行确定读取命令指定的数据是否被存储在主高速缓冲存储器中的处理（S8），以及当数据未被存储时在主缓存存储器（S8：否）中，执行判定数据是否存储在二次高速缓冲存储器中的处理（S9），并且当数据未存储在二次高速缓冲存储器中时（S9：否），执行处理从第一存储器读取数据的处理（S10），以及将数据存储在二级高速缓冲存储器和一级高速缓冲存储器中的处理（S13，S17）和将数据发送到总线主机的处理（S18）。

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