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1. 发明专利

JP2012059321A Resistance change memory device 有权
标题翻译：电阻变化存储器件
公开(公告)号：JP2012059321A
公开(公告)日：2012-03-22
申请号：JP2010201695
申请日：2010-09-09
申请人： Toshiba Corp , 株式会社東芝
发明人： UDA MIZUKI , SASAKI TAKAHIKO
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a resistance change memory device capable of setting a compliance current corresponding to each memory cell.SOLUTION: A current limit circuit includes a first current generation circuit, a second current generation circuit, and a determination circuit. The first current generation circuit stores a cell current of a first time as a storage current, and generates a first current having a current value obtained by being α times as large as the current value of the storage current. The second current generation circuit generates a second current having a current value obtained by being (β/α) times (α>β) as large as a cell current of a second time after the first time. The determination circuit outputs a control signal when determining that the current value of the second current exceeds the current value of the storage current. The first current generation circuit newly stores the storage current at timing based on the control signal.
摘要翻译：要解决的问题：提供一种能够设置与每个存储单元相对应的顺应性电流的电阻变化存储器件。解决方案：限流电路包括第一电流产生电路，第二电流产生电路和确定电路。第一电流产生电路将第一次的电池电流存储为存储电流，并且生成具有通过存储电流的当前值的α倍大得到的电流值的第一电流。第二电流产生电路产生具有与第一次之后第二次的电池电流一样大的（β/α）倍（α>β）获得的电流值的第二电流。当确定第二电流的当前值超过存储电流的当前值时，确定电路输出控制信号。第一电流产生电路基于控制信号在定时新存储电流。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012203946A Resistive ram 有权
标题翻译：电阻RAM
公开(公告)号：JP2012203946A
公开(公告)日：2012-10-22
申请号：JP2011066183
申请日：2011-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： UDA MIZUKI , AZUMA TOMOAKI , KUROSAWA TOMOKI
IPC分类号： G11C13/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2213/71 , G11C2213/72
摘要： PROBLEM TO BE SOLVED: To accurately change resistance of a memory cell.SOLUTION: A resistive RAM 1 comprises: multiple bit lines; multiple word lines; a memory cell array MA that includes multiple memory cells MC in which the bit lines and word lines are arranged at intersection parts and each of which includes a variable resistance element VR and a diode Di that are connected in series between the bit line and the word line; a control circuit that writes data in a selected memory cell by applying reverse bias to the diode Di; and a current limit circuit 25 that limits current flowed to the selected memory cell at the time of writing. The current limit circuit 25 controls the current flowed to a selected bit line so as not to exceed a second compliance current after adding a leakage current from a non-selected memory cell, which is connected to the selected bit line, to a predetermined first compliance current.
摘要翻译：要解决的问题：准确地改变存储单元的电阻。解决方案：电阻式RAM1包括：多个位线; 多个字线存储单元阵列MA，其包括多个存储单元MC，其中位线和字线布置在交叉部分，并且每个存储单元MC包括串联连接在位线和字之间的可变电阻元件VR和二极管Di 线; 控制电路，通过向二极管Di施加反向偏压来将数据写入选定的存储单元; 以及限制在写入时流向所选择的存储单元的电流的限流电路25。电流限制电路25控制流向所选位线的电流，以便将来自连接到所选位线的未选择存储单元的泄漏电流加到预定的第一顺从性之后不超过第二顺从电流当前。版权所有（C）2013，JPO＆INPIT

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