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1. 发明专利

JP2011151301A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011151301A
公开(公告)日：2011-08-04
申请号：JP2010013154
申请日：2010-01-25
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDAI TOMOKO , YASUHARA NORIO , SATO KUMIKO
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a logic-system CMOS transistor and a power DMOS transistor have optimum structures respectively. SOLUTION: The semiconductor device includes a first MOS transistor having a first source region 3, a drain region 4 and a first gate 13 provided on a top surface side of a first semiconductor region 2 and a first side wall 15 and a first LDD region 17 formed on both side faces of the first gate; and a second MOS transistor having a second source region 23, a drain region 24 and a second gate 33 provided on the top surface side of the second semiconductor region 22, a second side wall 41 formed on a side face of the second gate on the side of the second drain and being wider than the first side wall, a drift region 43 formed right below the second side wall, a third side wall 35 formed on a side face of the second gate on the side of a second source and being narrower than the first side wall, and a second LDD region 37 formed right below the third side wall. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种其中逻辑系统CMOS晶体管和功率DMOS晶体管分别具有最佳结构的半导体器件。解决方案：半导体器件包括第一MOS晶体管，其具有设置在第一半导体区域2的顶表面侧上的第一源极区域3，漏极区域4和第一栅极13，以及第一侧壁15和第一 LDD区域17形成在第一栅极的两个侧面上; 以及第二MOS晶体管，其具有设置在第二半导体区域22的顶面侧的第二源极区域23，漏极区域24和第二栅极33，形成在第二栅极的侧面上的第二侧壁41 并且比第一侧壁宽;在第二侧壁的正下方形成的漂移区域43，形成在第二栅极侧面上的第二源极的第三侧壁35，并且窄以及形成在第三侧壁正下方的第二LDD区域37。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2012023186A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012023186A
公开(公告)日：2012-02-02
申请号：JP2010159641
申请日：2010-07-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SATO KUMIKO , HIRASOZU KEISHI , MATSUDAI TOMOKO
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/1045 , H01L21/26513 , H01L21/26586 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a small variation in electrical properties due to process variation.SOLUTION: A semiconductor device comprises a first transistor 11 and a second transistor 12 that are formed on the top surface of a semiconductor substrate. The first and second transistors each include: a gate insulating film provided on the semiconductor substrate; a gate electrode 17 provided on the gate insulating film; a source region 21 and a drain region 22 of a second conductive type that are formed in regions sandwiching the region directly under the gate electrode at the upper part of the semiconductor substrate; and a high-concentration channel region of a first conductive type that is formed in a region near the source region side in the region directly under the gate electrode at the upper part of the semiconductor substrate and in which the effective impurity concentration is higher than that of the upper part. The directions toward the drain region from the source region of the first and second transistors are the same.
摘要翻译：要解决的问题：提供由于工艺变化而具有小的电特性变化的半导体器件。解决方案：半导体器件包括形成在半导体衬底的顶表面上的第一晶体管11和第二晶体管12。第一和第二晶体管各自包括：设置在半导体衬底上的栅极绝缘膜; 设置在栅极绝缘膜上的栅电极17; 第二导电类型的源极区域21和漏极区域22，形成在半导体衬底的上部的夹着栅电极正下方的区域的区域中; 以及形成在半导体衬底的上部的栅电极正下方的区域内的源极侧附近的区域中的有效杂质浓度高于其的有效杂质浓度的第一导电类型的高浓度沟道区域。的上部。从第一和第二晶体管的源极区朝向漏极区域的方向相同。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012004471A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012004471A
公开(公告)日：2012-01-05
申请号：JP2010140237
申请日：2010-06-21
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDAI TOMOKO , ENDO KOICHI , SATO KUMIKO , YASUHARA NORIO
IPC分类号： H01L29/78
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/0623 , H01L29/1045 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with little affection of process variation.SOLUTION: The semiconductor device comprises: a semiconductor substrate; a first conductive type region provided in an upper layer part of the semiconductor substrate; a second conductive type source region and a second conductive type drain region that are disposed apart from each other in an upper layer part of the first conductive region; a gate insulating film provided on the semiconductor substrate; and a gate electrode provided on the gate insulating film. In the first conductive type region, the effective impurity density in a channel region corresponding to the region directly below the gate electrode is highest at the boundary surface with the gate insulating film, and gradually decreases toward the lower portion.
摘要翻译：要解决的问题：为了提供对工艺变化几乎没有影响的半导体器件。解决方案：半导体器件包括：半导体衬底; 设置在所述半导体衬底的上层部分中的第一导电类型区域; 在第一导电区域的上层部分彼此分离设置的第二导电类型源极区域和第二导电型漏极区域; 设置在所述半导体基板上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。在第一导电型区域中，对应于栅电极正下方的区域的沟道区域中的有效杂质浓度在与栅极绝缘膜的边界面处最高，并且朝向下部逐渐减小。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011071171A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011071171A
公开(公告)日：2011-04-07
申请号：JP2009218762
申请日：2009-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUHARA NORIO , SATO KUMIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/417
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1087 , H01L29/41758 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of low on-resistance and high avalanche resistance. SOLUTION: The semiconductor device includes a first source portion S1 having a first source contact region 21 of a second conductivity type and a back gate contact region 22 of a first conductivity type; a second source portion S2 having a second source contact region 24 of the second conductivity type; and a drain portion D having a drain contact region 15 of the second conductivity type, a first drift region 16 of the second conductivity type formed on the first source contact region 21 side, and a second drift region 17 of the second conductivity type formed on the second source contact region 24 side, wherein the second drift region 17 has a length in the channel length direction longer than that of the first drift region 16. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种低导通电阻和高雪崩电阻的半导体器件。解决方案：半导体器件包括具有第二导电类型的第一源极接触区域21和第一导电类型的背栅极接触区域22的第一源极部分S1; 具有第二导电类型的第二源极接触区域24的第二源极部分S2; 以及具有第二导电类型的漏极接触区域15的漏极部分D，形成在第一源极接触区域21侧的第二导电类型的第一漂移区域16和形成在第二导电类型的第二导电类型的第二漂移区域17 第二源极接触区域24侧，其中第二漂移区域17具有比第一漂移区域16长的沟道长度方向上的长度。（C）2011年，JPO和INPIT

5. 发明专利

JP2007142041A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007142041A
公开(公告)日：2007-06-07
申请号：JP2005331742
申请日：2005-11-16
申请人： Toshiba Corp , 株式会社東芝
发明人： ENDO KOICHI , SATO KUMIKO , WATANABE KIMINORI , YASUHARA NORIO , MATSUDAI TOMOKO , KAWAGUCHI YUSUKE
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/0847 , H01L29/456 , H01L29/4933
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving both lowering of gate resistance and turning the breakdown strength of an element high. SOLUTION: A gate electrode 6 is formed on a semiconductor substrate 1 via a gate insulating film 5. Dispersion regions 2 and 3 are formed on the surface of the semiconductor substrate 1 so as to sandwich the gate electrode 6. A high resistance layer 21 is so formed on the surface of the semiconductor substrate 1 so as to be connected electrically to the diffusion region 3. A low resistance layer 22 is so formed on the surface of the semiconductor substrate 1 as to be connected electrically to the high resistance layer 21. A drain electrode 23 is connected to the low resistance layer 22. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够实现栅极电阻降低并且使元件的击穿强度变高的半导体器件。解决方案：通过栅极绝缘膜5在半导体衬底1上形成栅电极6.在半导体衬底1的表面上形成分散区域2和3，以夹着栅电极6.高电阻层21形成在半导体衬底1的表面上，以便与扩散区3电连接。低电阻层22形成在半导体衬底1的表面上，以电连接到高电阻漏极电极23连接到低电阻层22.版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2012134522A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012134522A
公开(公告)日：2012-07-12
申请号：JP2012034043
申请日：2012-02-20
申请人： Toshiba Corp , 株式会社東芝
发明人： YASUHARA NORIO , SATO KUMIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with low on-resistance and high avalanche resistance.SOLUTION: A semiconductor device of the present invention comprises: first source portions S1 each having first source contact regions 21 of a second conductivity type and a back-gate contact region 22 of a first conductivity type; second source portions S2 that have a second source contact region 24 of the second conductivity type and does not have the back-gate contact region of the first conductivity type; and drain portions D having a drain contact region 15 of the second conductivity type, a first drift region 16 of the second conductivity type formed at the first source contact region 21 side, and a second drift region 17 of the second conductivity type formed at the second source contact region 24 side. The length in the channel length direction of the second drift region 17 is longer than that of the first drift region 16.
摘要翻译：要解决的问题：提供具有低导通电阻和高雪崩电阻的半导体器件。解决方案：本发明的半导体器件包括：第一源极部分S1，其具有第一导电类型的第一源极接触区域21和第一导电类型的背栅极接触区域22; 第二源极部分S2具有第二导电类型的第二源极接触区域24，并且不具有第一导电类型的背栅极接触区域; 以及具有第二导电类型的漏极接触区域15的漏极部分D，形成在第一源极接触区域21侧的第二导电类型的第一漂移区域16和形成在第二导电类型的第二导电类型的第二漂移区域17 第二源极接触区域24侧。第二漂移区域17的通道长度方向的长度比第一漂移区域16的长度长。（C）2012，JPO＆INPIT

7. 发明专利

JP2011091231A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011091231A
公开(公告)日：2011-05-06
申请号：JP2009244117
申请日：2009-10-23
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDAI TOMOKO , YASUHARA NORIO , TSURUGAI TAKASHI , SATO KUMIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with low on-resistance. SOLUTION: The semiconductor device includes: a drain region 13 of a first conductivity type; a source region having a source layer 16 of the first conductivity type, a first back gate layer 17 and a second back gate layer 18 of a second conductivity type both; a channel region 15 of the second conductivity type arranged between the drain region 13 and the source region; a first semiconductor region 14 of the first conductivity type arranged between the drain region 13 and the channel region 15; and a second semiconductor region 19 of the first conductivity type arranged between the channel region 15 and the source region. The first back gate layer 17 is adjacent to the second semiconductor region 19 on one side of a channel length direction, and is adjacent to the source layer 16 on the other side of the channel length direction. Meanwhile, the second back gate layer 18 is adjacent to the source layer 16 on one side of the channel length direction, and is adjacent to the second semiconductor region 19 on the other side of the channel length direction. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有低导通电阻的半导体器件。解决方案：半导体器件包括：第一导电类型的漏极区域13; 具有第一导电类型的源极层16的源极区域，第二导电类型的第一背栅极层17和第二背栅极层18; 布置在漏极区域13和源极区域之间的第二导电类型的沟道区域15; 布置在漏极区域13和沟道区域15之间的第一导电类型的第一半导体区域14; 以及布置在沟道区域15和源极区域之间的第一导电类型的第二半导体区域19。第一背栅层17在沟道长度方向的一侧与第二半导体区域19相邻，并且与沟道长度方向另一侧的源极层16相邻。同时，第二背栅层18在沟道长度方向的一侧与源极层16相邻，并且与沟道长度方向另一侧的第二半导体区域19相邻。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010141006A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010141006A
公开(公告)日：2010-06-24
申请号：JP2008314291
申请日：2008-12-10
申请人： Toshiba Corp , 株式会社東芝
发明人： WARABINO TOMOYUKI , YASUHARA NORIO , HIRAHAYAMIZU KEIJI , MATSUDAI TOMOKO , YONEMURA KOJI , SATO KUMIKO , ENDO KOICHI , ISHIKAWA TAKASHI
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device containing a DMOS transistor with low on-state resistance.
SOLUTION: A CMOS transistor 1 is provided with a gate electrode 9, an N+ source region 3, and an N+ drain region 4. A DMOS transistor 21 is provided with a gate electrode 29, an N+ source region 23, an N- drift region 30, a drain region 24, and a silicide layer 32a. Sidewalls 8B are arranged on the side parts of the source region 3 side and the drain region side 4 side of the gate electrode 9. Sidewalls 28C and 28D are arranged on the side parts of the source region 23 side and the drain region 24 side of the gate electrode 29. The sidewall 28C of the drain region 24 side along the channel direction is thicker than the sidewall 28D and the sidewall 2B of the source region 23 side. Furthermore, the silicide layer 32a is formed up to the side edge of the drain region 24, on the upper surface of the gate electrode 9.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种制造包含具有低通态电阻的DMOS晶体管的半导体器件的方法。解决方案：CMOS晶体管1设置有栅电极9，N +源极区3和N +漏极区4.DMOS晶体管21设置有栅电极29，N +源极区23，N - 漂移区30，漏极区24和硅化物层32a。侧壁8B布置在栅极电极9的源极区域3侧和漏极区域侧侧的侧部上。侧壁28C和28D布置在源极区域23侧和漏极区域24侧的侧部栅极电极29.沿着沟道方向的漏极区域24侧的侧壁28C比源极区域23侧的侧壁28D和侧壁2B厚。此外，硅化物层32a形成在栅电极9的上表面上直到漏区24的侧边缘。版权所有（C）2010，JPO＆INPIT

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