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1. 发明专利

JP2010003914A Method for manufacturing solder bump 有权
标题翻译：制造焊接块的方法
公开(公告)号：JP2010003914A
公开(公告)日：2010-01-07
申请号：JP2008161959
申请日：2008-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO KYOKO , TOGASAKI TAKASHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/11 , H01L2224/11849 , H01L2224/11901 , H01L2224/13111 , H01L2924/01029 , H01L2224/11462
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing solder bumps, which can improve the accuracy in the weight ratio of Sn to Cu. SOLUTION: A resist layer 40 having an aperture 41 is formed on a UBM layer 30 formed on a semiconductor element 20, and a Cu plating layer 11 of which the thickness is substantially 0 is formed on the inner surface of the aperture 41 by an electric plating method; and after further forming an Sn plating layer 12 in the aperture 41, the resist layer 40 is removed, the UBM layer 30 is etched, and the Cu plating layer 11 and the Sn plating layer 12 are reflowed to form a solder bump of Sn-0.7Cu. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造焊锡凸块的方法，其可以提高Sn与Cu的重量比的精度。解决方案：在形成在半导体元件20上的UBM层30上形成具有孔41的抗蚀剂层40，并且在孔41的内表面上形成厚度基本为0的Cu镀层11 通过电镀法; 并且在孔41中进一步形成Sn镀层12之后，去除抗蚀剂层40，对UBM层30进行蚀刻，并且Cu镀层11和Sn镀层12回流以形成Sn- 0.7Cu钎。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2012069810A Manufacturing method of control module 有权
标题翻译：控制模块的制造方法
公开(公告)号：JP2012069810A
公开(公告)日：2012-04-05
申请号：JP2010214355
申请日：2010-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： ASAGIRI SATOSHI , KATO KYOKO , ITO YASUYUKI
IPC分类号： H05K3/28
CPC分类号： B29C43/18 , B29C39/10 , B29C70/70 , B29C2043/181 , H01L23/295 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce the amount of resin for sealing and facilitate the transportation to the next process.SOLUTION: In a manufacturing method of a control module, a substrate body 31 on which electronic components 32 and an aluminum electrolytic capacitor 33 are mounted is placed in a case 21 having an opening part 21a on an upper surface, and a filler 50 is injected into the case 21. The filler 50 is pressed from the front surface side by a jig 60, which has a recessed part 62 protruding upward to correspond to the aluminum electrolytic capacitor 33 located at a higher position relative to the substrate body 31 and covers the opening part 21a, and cured.
摘要翻译：要解决的问题：减少密封树脂的使用量，便于运输到下一个工序。解决方案：在控制模块的制造方法中，将其上安装有电子部件32和铝电解电容器33的基板主体31放置在具有在上表面上的开口部21a的壳体21中，并且填充物 50被注入到壳体21中。填料50被夹具60从前表面侧挤压，夹具60具有向上突出的凹部62，以对应于位于相对于基底主体31的较高位置的铝电解电容器33 并且覆盖开口部21a并固化。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011066346A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2011066346A
公开(公告)日：2011-03-31
申请号：JP2009217884
申请日：2009-09-18
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUCHI TOMOHIRO , HIGUCHI KAZUTO , KITANI TOMOYUKI , NISHIUCHI HIDEO , FUKUMITSU MASAKO , TOJO HIROSHI , KATO KYOKO
IPC分类号： H01L23/12
CPC分类号： H01L2224/34 , H01L2224/37599 , H01L2224/37647 , H01L2224/8385 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor device, in which further reduction in size of the device and reduction of internal resistance are attained while the effects of manufacturing at low cost and improvement of manufacturing efficiency are maintained. SOLUTION: A semiconductor device comprises: a semiconductor element 2; a first wiring layer 3 connected with a first electrode 2a on a side of a first surface A1; a second wiring layer 4 connected with a second electrode 2b at a side of a second surface A2; an insulating layer 5 provided around the semiconductor element 2 excluding the first surface A1 and the second surface A2; a through-hole 6 passing through the side of the first surface A1 and the side of the second surface A2 in the insulating layer 5; a third wiring layer 7 provided at the side of the first surface A1 and connected with the second wiring layer 4; external electrodes 8 provided on the first wiring layer 3 and the third wiring layer 7 respectively; and an enclosure 9 sealing the side of the second surface A2 including the second wiring layer 4 and sealing the periphery of the external electrodes 8 excluding an area exposed at the side of the first surface A1, the semiconductor element 2, the first wiring layer 3, and the third wiring layer 7. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：将要解决的问题：提供一种半导体器件和半导体器件的制造方法，其中，在制造成本低且制造性能提高的同时，实现器件尺寸的进一步减小和内阻的降低保持效率。解决方案：半导体器件包括：半导体元件2; 与第一面A1一侧的第一电极2a连接的第一布线层3; 与第二表面A2侧的第二电极2b连接的第二布线层4; 设置在除了第一面A1和第二面A2之外的半导体元件2周围的绝缘层5; 穿过绝缘层5中的第一表面A1侧和第二表面A2侧的通孔6; 设置在第一表面A1侧并与第二布线层4连接的第三布线层7; 设置在第一布线层3和第三布线层7上的外部电极8; 以及密封包括第二布线层4的第二表面A2的侧面并且密封外部电极8的外围的外壳9，除了暴露在第一表面A1，半导体元件2，第一布线层3 ，和第三布线层7.版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011216713A Resin-sealing method for mounting substrate 审中-公开
标题翻译：用于安装基板的树脂密封方法
公开(公告)号：JP2011216713A
公开(公告)日：2011-10-27
申请号：JP2010084317
申请日：2010-03-31
申请人： Toshiba Corp , 株式会社東芝
发明人： ASAGIRI SATOSHI , KATO KYOKO
IPC分类号： H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a resin-sealing method for a mounting substrate that is high in reliability under a normal pressure or reduced pressure.SOLUTION: The resin-sealing method for the mounting substrate 1 in which the mounting substrate 1 mounted with an electronic component 4 is resin-sealed in a case 2 with a resin 7 is characterized in that the mounting substrate 1 is provided with an bubble generation preventing tool.
摘要翻译：要解决的问题：提供一种在常压或减压下可靠性高的安装基板的树脂密封方法。解决方案：安装基板1的树脂密封方法，其中安装基板1安装有电子部件4树脂密封在具有树脂7的壳体2中的特征在于，安装基板1设置有气泡发生防止工具。

5. 发明专利

JP2011211107A Method of resin-sealing mounting substrate 有权
标题翻译：树脂密封安装方法
公开(公告)号：JP2011211107A
公开(公告)日：2011-10-20
申请号：JP2010079816
申请日：2010-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO KYOKO , ASAGIRI SATOSHI
IPC分类号： H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a reliable resin-sealing method that is performed under an ordinary pressure or a diminished pressure.SOLUTION: The method of resin-sealing a mounting board for sealing a mounting substrate 1 with an electronic part 4 mounted on a substrate body 3 in a case 2 by using a resin 8, wherein the resin 8 is filled into the case 2 via a slope 5 under ordinary pressure or diminished pressure. The slope 5 is disposed on a space S between a sidewall 2b of the case 2 and an end of the mounting substrate 1.
摘要翻译：要解决的问题：提供在常压或减压下进行的可靠的树脂密封方法。解决方案：将安装基板1进行树脂密封的方法，安装基板1安装在安装基板1上的电子部件4 通过使用树脂8在壳体2中的基板主体3，其中树脂8在常压或减压下经由斜面5填充到壳体2中。斜面5设置在壳体2的侧壁2b和安装基板1的端部之间的空间S上。

6. 发明专利

JP2010087490A Semiconductor device and semiconductor device manufacturing method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2010087490A
公开(公告)日：2010-04-15
申请号：JP2009201415
申请日：2009-09-01
申请人： Toshiba Corp , 株式会社東芝
发明人： TOJO HIROSHI , KITANI TOMOYUKI , HIGUCHI KAZUTO , OISHI MASAKO , IGUCHI TOMOHIRO , NISHIUCHI HIDEO , KATO KYOKO
IPC分类号： H01L23/48
CPC分类号： H01L24/97 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/544 , H01L24/03 , H01L24/48 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/274 , H01L2224/48091 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19041 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which improves an electric characteristic and keeps high reliability by means of a structure without using a bonding wire, and which can improve a productivity by removing a laser machining process and shortening a manufacturing time, and to provide its manufacturing method. SOLUTION: The semiconductor device includes a semiconductor chip 2 in which a first electrode 2a1 is located on a first surface 2a and a second electrode 2b1 is located on a second surface 2b opposed to the first surface 2a, a sealing component 3 which exposes only areas of the first electrode 2a1 and second electrode 2b1 to seal the other surface of the semiconductor chip 2, an internal electrode 4 which is connected with the first electrode 2a1 or the second electrode 2b1, and a thickness from the first surface 2a and second surface 2b is the same as the thickness of the sealing component 3, an external electrode 5 which is connected with the internal electrode 4, is formed on the sealing component 3 too, and is at least wider than the width of the semiconductor chip 2, and external plating films 6 which cover five surfaces except for the surface of the external electrode 5 connected with the internal electrode 4. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过不使用接合线的结构提高电特性并保持高可靠性的半导体器件，并且可以通过去除激光加工过程并缩短制造时间来提高生产率并提供其制造方法。解决方案：半导体器件包括半导体芯片2，其中第一电极2a1位于第一表面2a上，第二电极2b1位于与第一表面2a相对的第二表面2b上，密封部件3 仅露出第一电极2a1和第二电极2b1的区域，以密封半导体芯片2的另一个表面，与第一电极2a1或第二电极2b1连接的内部电极4和来自第一表面2a和第二表面2b与密封部件3的厚度相同，与内部电极4连接的外部电极5也形成在密封部件3上，并且至少比半导体芯片2的宽度宽，以及外部电镀膜6，其覆盖与内部电极4连接的外部电极5的表面以外的五个表面。（C）2010，JPO＆INPIT

7. 发明专利

JP2010225951A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2010225951A
公开(公告)日：2010-10-07
申请号：JP2009073047
申请日：2009-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIUCHI HIDEO , HIGUCHI KAZUTO , KITANI TOMOYUKI , IGUCHI TOMOHIRO , FUKUMITSU MASAKO , TOJO HIROSHI , KATO KYOKO
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/97 , H01L2224/13
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has high insulation performance and high strength while maintaining such an effect as the miniaturization of the device, more reduction in the resistance of an internal resistance, manufacturing at low cost, and improvement in manufacturing efficiency, and a method of manufacturing the semiconductor device. SOLUTION: The device has a substrate 2 in which a source electrode S and a gate electrode G are prepared in a first surface S1, and a drain electrode D is prepared in a second surface S2, a first wiring layer 3 which is connected to the source electrode S prepared on the first surface S1, a second wiring layer 4 which is prepared on the first surface S1, and connected to the drain electrode D, copper posts 5 prepared on the first wiring layer 3 and on the second wiring layer 4, respectively, a third wiring layer 6 which is connected to the drain electrode D prepared on the second surface S2, a through-hole 7 which penetrates the substrate 2, and establishes conduction between the second wiring layer 4 and the third wiring layer 6, and an enclosure 9 in which only a first facing surface and a second facing surface of the copper post 5 are exposed, and the first wiring layer 3, the second wiring layer 4, the third wiring layer 6 and the substrate 2 are sealed. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种具有高绝缘性能和高强度的半导体器件，同时保持了器件的小型化的效果，内阻的电阻更多的降低，低成本的制造和改进的制造效率，以及半导体装置的制造方法。解决方案：器件具有在第一表面S1中制备源电极S和栅极电极G的衬底2，并且在第二表面S2中制备漏电极D，第一布线层3 连接到在第一表面S1上制备的源电极S，制备在第一表面S1上并连接到漏电极D的第二布线层4，在第一布线层3上准备的铜柱5和第二布线层4分别连接到在第二表面S2上制备的漏电极D的第三布线层6，穿透基板2的通孔7，并且在第二布线层4和第三布线层之间建立导通 6以及仅露出铜柱5的第一面对面和第二面对面的壳体9，并且第一配线层3，第二配线层4，第三配线层6和基板2被密封。版权所有（C）2011，JPO＆INPIT

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